multi8x8.vhd

实现了VHDL乘法器

library ieee;
use ieee.std_logic_1164.all;
entity multi8x8 is port(
    clk : in std_logic;
  start : in std_logic;
      a : in std_logic_vector(7 downto 0);
      b : in std_logic_vector(7 downto 0);
 ariend : out std_logic;
   dout : out std_logic_vector(15 downto 0));
end multi8x8;
architecture struc of multi8x8 is
component arictl port(
    clk : in std_logic;
  start : in std_logic;
 clkout : out std_logic;
 rstall : out std_logic;
 ariend : out std_logic);
end component;
component andarith port(
   abin : in std_logic;
    din : in std_logic_vector(7 downto 0);
   dout : out std_logic_vector(7 downto 0));
end component;
component adder8b port(
    cin : in std_logic;
      a : in std_logic_vector(7 downto 0);
      b : in std_logic_vector(7 downto 0);
      s : out std_logic_vector(7 downto 0);
   cout : out std_logic);
end component;
component sreg8b port(
    clk : in std_logic;
   load : in std_logic;
    din : in std_logic_vector(7 downto 0);
     qb : out std_logic);
end component;
component reg16b port(
    clk : in std_logic;
    clr : in std_logic;
      d : in std_logic_vector(8 downto 0);
      q : out std_logic_vector(15 downto 0));
end component;
   signal gndint, intclk, rstall, qb : std_logic;
   signal andsd : std_logic_vector(7 downto 0);
   signal dtbin : std_logic_vector(8 downto 0);
   signal dtbout: std_logic_vector(15 downto 0);   
begin
   dout <= dtbout; gndint <= '0';
   u1: arictl port map(clk, start, intclk, rstall, ariend);
   u2: sreg8b port map(intclk, rstall, b, qb);
   u3: andarith port map(qb, a, andsd);
   u4: adder8b port map(gndint, dtbout(15 downto 8),andsd, dtbin(7 downto 0), dtbin(8));
   u5: reg16b port map(intclk, rstall, dtbin, dtbout);
end struc;