adder4b.vhd

来自「实现了VHDL乘法器」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4b is port(
     cin : in std_logic;
       a : in std_logic_vector(3 downto 0);
       b : in std_logic_vector(3 downto 0);
       s : out std_logic_vector(3 downto 0);
    cout : out std_logic);
end adder4b;
architecture one of adder4b is
signal aa,bb,sint : std_logic_vector(4 downto 0);
begin
   aa <= '0'&a ;
   bb <= '0'&b ;
   sint <= aa + bb + cin ;
   s <= sint(3 downto 0) ;
   cout <=sint(4);
end one;