contral.vhd

用VHDL实现频率计

-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY contrOl IS

	PORT
	(
		clk		: IN	STD_LOGIC;
		EN,LD,RST		: OUT 	STD_LOGIC
	);
	
END contrOl;

ARCHITECTURE a OF contrOl IS
SIGNAL ENINSIDE : STD_LOGIC;
BEGIN
EN<=ENINSIDE;
LD<=NOT ENINSIDE;
RST<=(NOT CLK)AND(NOT ENINSIDE);
PROCESS (CLK)
BEGIN
 IF clk'EVENT AND clk = '1'THEN
	ENINSIDE<=NOT ENINSIDE;
END IF;
END PROCESS;
END A;