📄 bel.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bel is
port(ms1,ss1:in std_logic_vector(7 downto 4);
ms2,ss2:in std_logic_vector(3 downto 0);
bell: out std_logic;
cpt,f512,f1024:in std_logic);
end bel;
architecture belx of bel is
signal m0,n0: std_logic;
begin
process(m0,n0,ms1,ms2,ss1,ss2)
begin
if cpt='1' then
m0<=f512;
n0<='0';
elsif(ms1=5 and ms2=9 and ss1=5 and cpt='0')then
if(ss2=1 or ss2=3 or ss2=5 or ss2=7)then
m0<='0';
n0<=f512;
elsif ss2=9 then
m0<='0';
n0<=f1024;
end if;
end if;
end process;
bell<=m0 or n0;
end belx;
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