代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/412239/11208955
vhd arm7tdmis_top.vhd
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
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vhd multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
--*********
www.eeworm.com/read/412187/11211346
vhd ctl_1.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_1 is
Port(
wr :in std_logic; -- 作时钟使用
A :in std_logic_vector(15 downto 0); -- 16位地址线
D :in std_logic_vector(7 downto 0); --
www.eeworm.com/read/412187/11211349
vhd ctl_2.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_2 is
Port(
clk :in std_logic; -- 作时钟使用
P1_0 :in std_logic; -- 控制脉冲宽度
T :in std_logic_vector(19 downto 0); -- 20位中间控制信号
Q :
www.eeworm.com/read/266571/11219594
vhd txunit.vhd
-------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
---------------------------------------------------------------------------
www.eeworm.com/read/411428/11245905
vhd top_date_clock.vhd
----------------------------------------------------------------------------------------------------
--This module used as a date-clock counter,it can count second,minute,hour,day,month,year
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vhd counter104.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter104 is
Port ( set,rd : in std_logic;
clk : in std_logic;
www.eeworm.com/read/411380/11247795
vhd counter2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter2 is
Port ( set,rd : in std_logic;
clk : in std_logic;
www.eeworm.com/read/411380/11247796
vhd sztop.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sztop is
Port ( clk1,sz: in std_logic;
ringg:out std_logic;
h1
www.eeworm.com/read/411380/11247797
vhd counter10.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( set : in std_logic;
clk : in std_logic;