sztop.vhd

采用VHDL语言设计了一个打铃系统。该系统已经调试

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sztop is
    Port ( clk1,sz: in std_logic;
	        ringg:out std_logic;
	 h1 : in std_logic_vector(3 downto 0);
	 h0 : in std_logic_vector(3 downto 0);
	 m1 : in std_logic_vector(3 downto 0);
	 m0 : in std_logic_vector(3 downto 0);
	 s1 : in std_logic_vector(3 downto 0);
	 s0 : in std_logic_vector(3 downto 0);
	 hour1 : out std_logic_vector(6 downto 0);
	 hour0 : out std_logic_vector(6 downto 0);
	 min1 : out std_logic_vector(6 downto 0);
	 min0 : out std_logic_vector(6 downto 0);
	 sec1 : out std_logic_vector(6 downto 0);
    sec0 : out std_logic_vector(6 downto 0));
end sztop;

architecture Behavioral of sztop is

component counter10
Port ( set : in std_logic;
           clk : in std_logic;
           x : in std_logic_vector(3 downto 0);
           y : out std_logic_vector(3 downto 0);
           c : out std_logic);
			  end component;
component counter104
Port ( set,rd : in std_logic;
           clk : in std_logic;
           x : in std_logic_vector(3 downto 0);
           y : out std_logic_vector(3 downto 0);
           c,k : out std_logic);
			  end component;
component counter2
Port ( set,rd : in std_logic;
           clk : in std_logic;
           x : in std_logic_vector(3 downto 0);
           y : out std_logic_vector(3 downto 0);
           c : out std_logic);
			  end component;
 component counter6
 Port ( set : in std_logic;
           clk : in std_logic;
           x : in std_logic_vector(3 downto 0);
           y : out std_logic_vector(3 downto 0);
           c : out std_logic);
			  end component;
 component decoder
 Port (seg:in std_logic_vector(3 downto 0 );
	       q3:out std_logic_vector(6 downto 0)
			 );
			  end component;
 component pulse
  Port ( clock,en:in std_logic;
	 clk:out std_logic
	 );
			  end component;
 component and2
 Port ( a : in std_logic;
           b : in std_logic;
           c : out std_logic);
			  end component;
component adder 
  port(reset1:in std_logic;
	       clina1:in std_logic_vector(3 downto 0);
			 clinb1:in std_logic_vector(3 downto 0);
	       mina1:in std_logic_vector(3 downto 0);
			 minb1:in std_logic_vector(3 downto 0);
			 sina1:in std_logic_vector(3 downto 0);
			 sinb1:in std_logic_vector(3 downto 0);
			 zout1:out integer
			 );
            end component;
component ring
   port(ringing2:out std_logic;
			 clock2:in std_logic;
			 dclk2:in integer;
			 reset2:in std_logic
			 );
end component;

signal sh1,sh0,sm1,sm0,ss1,ss0:std_logic_vector(3 downto 0);
signal ca,cb,cc,cd,ce,cf,ch,ci,sand1,sand2,sign2:std_logic;
signal sign1:integer;

begin
u1:pulse port map(clock=>clk1,en=>sz,clk=>ca);
u2:counter10 port map(clk=>ca,set=>sz,x=>s0,y=>ss0,c=>cb);
u3:counter6 port map(clk=>cb,set=>sz,x=>s1,y=>ss1,c=>cc);
u4:counter10 port map(clk=>cc,set=>sz,x=>m0,y=>sm0,c=>cd);
u5:counter6 port map(clk=>cd,set=>sz,x=>m1,y=>sm1,c=>ce);
u6:counter104 port map(clk=>ce,set=>sz,x=>h0,y=>sh0,c=>cf,rd=>ci,k=>sand1);
u7:counter2 port map(clk=>cf,set=>sz,x=>h1,y=>sh1,c=>sand2,rd=>ci);
u8:and2 port map(a=>sand1,b=>sand2,c=>ci);
u9:decoder port map(seg=>ss0,q3=>sec0);
u10:decoder port map(seg=>ss1,q3=>sec1);
u11:decoder port map(seg=>sm0,q3=>min0);
u12:decoder port map(seg=>sm1,q3=>min1);
u13:decoder port map(seg=>sh0,q3=>hour0);
u14:decoder port map(seg=>sh1,q3=>hour1);
u15:adder port map(reset1=>sz,clina1=>h0,clinb1=>h1,
                   mina1=>m0,minb1=>m1,sina1=>s0,sinb1=>s1,zout1=>sign1);
u16:ring port map(reset2=>sz,clock2=>sign2,dclk2=>sign1,ringing2=>ringg);
u17:pulse port map(clock=>clk1,en=>sz,clk=>sign2);

end Behavioral;