📄 top_date_clock.vhd
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--This module used as a date-clock counter,it can count second,minute,hour,day,month,year --
--and identify month has 28,29,30 or 31 days by identiying whether the year is leap-year or not --
--Through port preset_second,preset_minute,preset_hour,iday_cntl,iday_cnth,imonth_cnth,iyear_cntl --
--iyear_cntml,iyear_cntmh,iyear_cnth to preset second,minute,hour,day,month and year. --
--This top module consist of 2 big modules:clock and date_counter. --
--Port clk_1Hz (1Hz frequence to drive clock) --
--Port start (when start is '0' then preset enable,when start is '1' it is started) --
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_date_clock is
Port ( clk:in std_logic;
reset: in std_logic;
reset_statemachine:in std_logic;
reset_lcd:in std_logic;
reset_counter:in std_logic;
buttonr:in std_logic;
buttonl:in std_logic;
add : in std_logic;--频率增加键
sub : in std_logic;--频率减小键
preset_enable:in std_logic;
convert:in std_logic_vector(1 downto 0);
RA: out std_logic_vector(5 downto 0);--分频预置数输出
RN: out std_logic_vector(9 downto 0);
--pulse :in std_logic;
--show: out std_logic;
--flag: out std_logic;
TXD : out std_logic);
end top_date_clock;
architecture Behavioral of top_date_clock is
component clock
Port ( clk_1Hz:in std_logic;
clock_reset : in std_logic;
preset_second : in std_logic_vector(7 downto 0);
preset_minute : in std_logic_vector(7 downto 0);
preset_hour : in std_logic_vector(7 downto 0);
out_second : out std_logic_vector(7 downto 0);
out_minute : out std_logic_vector(7 downto 0);
out_hour : out std_logic_vector(7 downto 0);
out_carry : out std_logic );
end component;
component date_counter
Port ( reset: in std_logic;
clk_day : in std_logic;
iday_cntl : in std_logic_vector(3 downto 0);
iday_cnth : in std_logic_vector(3 downto 0);
imonth_cntl : in std_logic_vector(3 downto 0);
imonth_cnth : in std_logic_vector(3 downto 0);
iyear_cntl : in std_logic_vector(3 downto 0);
iyear_cntml : in std_logic_vector(3 downto 0);
iyear_cntmh : in std_logic_vector(3 downto 0);
iyear_cnth : in std_logic_vector(3 downto 0);
oday_cntl : out std_logic_vector(3 downto 0);
oday_cnth : out std_logic_vector(3 downto 0);
omonth_cntl : out std_logic_vector(3 downto 0);
omonth_cnth : out std_logic_vector(3 downto 0);
oyear_cntl : out std_logic_vector(3 downto 0);
oyear_cntml : out std_logic_vector(3 downto 0);
oyear_cntmh : out std_logic_vector(3 downto 0);
oyear_cnth : out std_logic_vector(3 downto 0));
end component;
component clk_generator
Port ( clk : in std_logic;
clk_1Hz : out std_logic;
clk_statemachine : out std_logic;
pulse :out std_logic);
end component;
component statemachine
Port ( reset : in std_logic;
buttonr : in std_logic;
buttonl : in std_logic;
preset_enable : in std_logic;
clk : in std_logic;
clk_1Hz:in std_logic;
--flag: out std_logic;
flash1: out std_logic_vector(3 downto 0);
day_cntl : out std_logic_vector(3 downto 0);
day_cnth : out std_logic_vector(3 downto 0);
month_cntl : out std_logic_vector(3 downto 0);
month_cnth : out std_logic_vector(3 downto 0);
year_cntl : out std_logic_vector(3 downto 0);
year_cntml : out std_logic_vector(3 downto 0);
year_cntmh : out std_logic_vector(3 downto 0);
year_cnth : out std_logic_vector(3 downto 0);
hour_cntl : out std_logic_vector(3 downto 0);
hour_cnth : out std_logic_vector(3 downto 0);
minute_cntl : out std_logic_vector(3 downto 0);
minute_cnth : out std_logic_vector(3 downto 0);
second_cntl : out std_logic_vector(3 downto 0);
second_cnth : out std_logic_vector(3 downto 0);
count_dayh : out std_logic_vector(3 downto 0);
count_dayl : out std_logic_vector(3 downto 0);
count_hourh : out std_logic_vector(3 downto 0);
count_hourl: out std_logic_vector(3 downto 0);
count_minuteh: out std_logic_vector(3 downto 0);
count_minutel : out std_logic_vector(3 downto 0);
how_many_hourh : out std_logic_vector(3 downto 0);
how_many_hourl : out std_logic_vector(3 downto 0));
end component;
component comparator
Port ( dayh : in std_logic_vector(3 downto 0);
dayl : in std_logic_vector(3 downto 0);
hourh : in std_logic_vector(3 downto 0);
hourl : in std_logic_vector(3 downto 0);
minutel:in std_logic_vector(3 downto 0);
minuteh:in std_logic_vector(3 downto 0);
input_dayh : in std_logic_vector(3 downto 0);
input_dayl : in std_logic_vector(3 downto 0);
input_hourh : in std_logic_vector(3 downto 0);
input_hourl : in std_logic_vector(3 downto 0);
input_minuteh : in std_logic_vector(3 downto 0);
input_minutel : in std_logic_vector(3 downto 0);
count_hours : in std_logic_vector(7 downto 0);
output_star : out std_logic);
end component;
component gate_and2
Port ( in1 : in std_logic;
in2 : in std_logic;
out1 : out std_logic);
end component;
component counter
Port ( reset:in std_logic;
clk : in std_logic;
outh : out std_logic_vector(3 downto 0);
outmh : out std_logic_vector(3 downto 0);
outml:out std_logic_vector(3 downto 0);
outl:out std_logic_vector(3 downto 0));
end component;
component data_send
Port (sysclk,reset:in std_Logic;
data0,data1,data2,data3,data4,data5,data6,data7, data8,data9,data10,data11,data12,data13,data14,data15,data16,data17,data18,data19,data20,data21 : in std_logic_vector(3 downto 0);
TXD :out std_logic);
end component;
component ssend
Port ( clk,reset : in std_logic;
add : in std_logic;--频率增加键
sub : in std_logic;--频率减小键
convert:in std_logic_vector(1 downto 0);
data0,data1,data2,data3,data4,data5 :out std_logic_vector(3 downto 0 );
A: out std_logic_vector(5 downto 0);--分频预置数输出
N: out std_logic_vector(9 downto 0));--分频预置数输出
end component;
signal tempcarry,clk_1Hz,clk_statemachine,temp1,temp2,temp3,clk_reset_p:std_logic;
signal a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z:std_logic_vector(3 downto 0);
signal aa,bb,cc,dd,ee,ff,gg,hh,ii,jj,kk,ll,mm,nn,ooo,data15p,data16p,data17p,data18p,data19p,data20p,data21p:std_logic_vector(3 downto 0);
signal aaa,bbb,ccc,ddd,eee,fff,ggg,hhh,iii,jjj,kkk,lll,mmm,nnn,oo,pp,qq,rr,ss,tt,uu,vv,ww,xx,yy,zz:std_logic_vector(7 downto 0);
signal flash:std_logic_vector(3 downto 0);
begin
u0:clk_generator port map(clk=>clk,clk_1Hz=>clk_1Hz,clk_statemachine=>clk_statemachine,pulse=>temp3);
u1:statemachine port map(buttonl=>buttonl,reset=>reset_statemachine,buttonr=>buttonr,preset_enable=>preset_enable,clk=>clk_statemachine,
year_cnth=>a,year_cntmh=>b,year_cntml=>c,year_cntl=>d,month_cnth=>e,month_cntl=>f,clk_1Hz=>clk_1Hz,
day_cnth=>g,day_cntl=>h,hour_cnth=>i,hour_cntl=>j,minute_cnth=>k,minute_cntl=>l,
second_cnth=>m,second_cntl=>n,count_minuteh=>s,count_minutel=>t,
count_dayh=>o,count_dayl=>p,count_hourh=>q,count_hourl=>r,
how_many_hourh=>u,how_many_hourl=>v,flash1=>flash);
u2:clock port map(clk_1Hz=>clk_1Hz,clock_reset=>preset_enable,preset_second(7 downto 4)=>m,preset_second(3 downto 0)=>n,
preset_minute(7 downto 4)=>k,preset_minute(3 downto 0)=>l,
preset_hour(7 downto 4)=>i,preset_hour(3 downto 0)=>j,
out_second(7 downto 4)=>mm,out_second(3 downto 0)=>nn,out_minute(7 downto 4)=>kk,
out_minute(3 downto 0)=>ll,out_hour(7 downto 4)=>ii,out_hour(3 downto 0)=>jj,out_carry=>tempcarry);
u3:date_counter port map(reset=>preset_enable,clk_day=>tempcarry,iyear_cnth=>a,iyear_cntmh=>b,iyear_cntml=>c,
iyear_cntl=>d,imonth_cnth=>e,imonth_cntl=>f,iday_cnth=>g,iday_cntl=>h,
oyear_cnth=>aa,oyear_cntmh=>bb,oyear_cntml=>cc,oyear_cntl=>dd,
omonth_cnth=>ee,omonth_cntl=>ff,oday_cnth=>gg,oday_cntl=>hh);
u4:data_send port map (sysclk=>clk,reset=>reset,data0=>aa,data1=>bb,data2=>cc,data3=>dd,
data4=>ee,data5=>ff,data6=>gg,data7=>hh,data8=>ii,data9=>jj,data10=>kk,data11=>ll,
data12=>mm,data13=>nn,data14=>flash,data15=>data15p,data16=>data16p,data17=>data17p,
data18=>data18p,data19=>data19p,data20=>data20p,data21=>data21p,TXD=>TXD);
u27:comparator port map(dayh=>gg,dayl=>hh,hourh=>ii,hourl=>jj,minuteh=>kk,minutel=>ll,
input_dayh=>o,input_dayl=>p,input_hourh=>q,input_hourl=>r,
input_minuteh=>s,input_minutel=>t,count_hours(7 downto 4)=>u,
count_hours(3 downto 0)=>v,output_star=>temp1);
u28:gate_and2 port map(in1=>temp3,in2=>temp1,out1=>temp2);
u29:counter port map(reset=>reset_counter,clk=>temp2,outh=>w,outmh=>x,outml=>y,outl=>z);
u30:ssend port map (clk=>clk,reset=>reset,data0=>data15p,data1=>data16p,data2=>data17p,data3=>data18p,
data4=>data19p,data5=>data20p,A=>RA,N=>RN,add=>add,sub=>sub,convert=>convert);
end Behavioral;
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