📄 counter10.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( set : in std_logic;
clk : in std_logic;
x:in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0);
c : out std_logic);
end counter10;
architecture Behavioral of counter10 is
begin
process(set,x,clk)
variable cnt:std_logic_vector(3 downto 0);
begin
if set= '0' then
cnt:=x;
y<=cnt;c<='0';
elsif clk'event and clk='1' then
if cnt="1001" then
cnt:="0000";y<=cnt;c<='1';
else cnt:=cnt+1;y<=cnt;c<='0';
end if;
end if;
end process;
end Behavioral;
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