counter2.vhd

来自「采用VHDL语言设计了一个打铃系统。该系统已经调试」· VHDL 代码 · 共 35 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter2 is
    Port ( set,rd : in std_logic;
           clk : in std_logic;
           x : in std_logic_vector(3 downto 0);
           y : out std_logic_vector(3 downto 0);
           c : out std_logic);
end counter2;

architecture Behavioral of counter2 is

   begin
       process(set,clk,x,rd)
            variable cnt:std_logic_vector(3 downto 0);
      begin
        if rd='1' then cnt:="0000";y<="0000";c<='0';
        elsif set='0' then 
                 cnt:=x;
                 y<=cnt;c<='0';

        elsif clk'event and clk='1' then

              if cnt="0010" then
                 cnt:="0000";y<=cnt;c<='0';
              elsif cnt="0001" then cnt:=cnt+1;y<=cnt;c<='1';
              else cnt:=cnt+1;y<=cnt;c<='0';
              end if;
        end if;
end process;
end Behavioral;