代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/481069/6657411
txt 58.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c_k is
port( CLK : in std_logic;
c_out: out std_logic);
end c_k;
architecture c_mk of c_k is
signal C
www.eeworm.com/read/480769/6661401
vhd picoblaze_real_time_clock.vhd
--
-- Reference design - Real Time Clock and Calendar
--
-- Modified By George Wang.
--
-- The design is based on 's2esk_startup' (the initial design for Spartan-3E
-- Starter Kit when delivere
www.eeworm.com/read/479086/6699208
vhd cnt.vhd
library ieee;
use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity cnt is
port(in_clk,en,rst: in std_logic;
CQ: out std_logic_vector(3 downto 0);
cout:out std_
www.eeworm.com/read/478303/6714456
vhd gcd.vhd
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity gcd is
port( a,b:in std_logic_vector(7 downto 0);
CLK,RST,START:in std_logic;
c:ou
www.eeworm.com/read/478303/6714472
vhd ex_p3_18_factorial.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FACTORIAL is
port(A : in STD_LOGIC_VECTOR(3 downto 0);
F :out STD_LOGIC_VECTOR(31 downto 0);
ST_A,
www.eeworm.com/read/478303/6714501
vhd ex_5_10_libram.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
LIBRARY unisim;
use unisim.VCOMPONENTS.all;
entity libcomp is
Port ( DIN : in STD_LOGIC_VECTOR (7 downto 0);
ENBL : in STD_ULOGIC;
www.eeworm.com/read/478253/6722755
vhd division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
www.eeworm.com/read/478253/6722767
vhd usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
www.eeworm.com/read/478253/6722768
vhd led.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
port(
A : in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
WR : in STD_LOGIC; -- 写使能
DWR : in STD_LOGIC_VECTOR(
www.eeworm.com/read/478253/6722831
vhd txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto