ex_5_10_libram.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 31 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
LIBRARY unisim;
use unisim.VCOMPONENTS.all;
entity libcomp is
    Port ( 	DIN    : in STD_LOGIC_VECTOR (7 downto 0);
        		ENBL   : in STD_ULOGIC;
        		WE     : in STD_ULOGIC;
        		RESET  : in STD_ULOGIC;
        		CLOCK  : in STD_ULOGIC;
        		ADR    : in STD_LOGIC_VECTOR (8 downto 0);
        		DOUT   : out STD_LOGIC_VECTOR (7 downto 0)); 
end libcomp;

architecture Behavioral of libcomp is
	signal bufclk:std_logic;
begin
	U1:BUFG   port map(bufclk,clock);
	RAM:RAMB4_S8 port map(
	      DI=>din,EN=>enbl,WE=>we,
	      RST=>reset,CLK=>bufclk,
	      ADDR=>adr,DO=>dout);
   --DO : out STD_LOGIC_VECTOR (7 downto 0);
	--ADDR : in STD_LOGIC_VECTOR (8 downto 0);
	--CLK : in STD_ULOGIC;
	--DI : in STD_LOGIC_VECTOR (7 downto 0);
	--EN : in STD_ULOGIC;
	--RST : in STD_ULOGIC;
	--WE : in STD_ULOGIC

end Behavioral;