代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/307202/13726884
vhd lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --3.125MHZ FROM div16 Module
www.eeworm.com/read/307153/13727457
txt light.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity light is
port(clk:in std_logic;
q1:out std_logic_vector(5 downto 0));
end
www.eeworm.com/read/307079/13731692
vhd aa.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aa is
port( a: in unsigned(3 downto 0);
b: in unsigned(3 downto 0);
cin:in
www.eeworm.com/read/307021/13732866
vhd addern8.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity addern8 Is
GENERIC(datawidth:Integer:=8);
port(
cin : in std_logic;
a: in std_logic_vector(datawidth-1
www.eeworm.com/read/307021/13732896
vhd mux3_8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux3_8 is PORT(
a, b, c, d,e,f,g,h: IN STD_LOGIC; --输入8路。
s: IN STD_LOGIC_VECTOR(2 DOWNTO 0); --地址信号
www.eeworm.com/read/307021/13732904
vhd and8.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and8 IS
PORT(
a1,a2,a3,a4,a5,a6,a7,a8 : IN STD_LOGIC;
y : OUT STD_LOGIC);
END and8;
ARCHITECTURE behavier OF and8 IS
BEGIN
y
www.eeworm.com/read/307021/13732918
vhd freqdetect_top.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY freqdetect_top IS
PORT(clk : IN STD_LOGIC; --clk时钟
sign : IN STD_LOGIC; --待测信
www.eeworm.com/read/306474/13744737
txt plus.txt
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
entity add is
port
(
x:in std_logic_vector(3 downto 0); --部分积1011
s:in std_logic_vector(3 downto 0); --pA1011
l:in std_logic; --单个乘数0
m
www.eeworm.com/read/306208/13749240
vhd my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
www.eeworm.com/read/306208/13749243
vhd shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i