addern8.vhd

来自「这是一些经典的vhdl example」· VHDL 代码 · 共 37 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity addern8 Is
	GENERIC(datawidth:Integer:=8);
	port(
			cin : in std_logic;
			a: in std_logic_vector(datawidth-1 downto 0);
			b: in std_logic_vector(datawidth-1 downto 0);
			sum:out std_logic_vector(datawidth-1 downto 0);
			cout:out std_logic
		);
end addern8;
architecture rtl of addern8 is
	component adder
        port (a    : in std_logic;
              b    : in std_logic;
              cin  : in std_logic;
              s  : out std_logic;
              cout : out std_logic);
    end component;
    signal carry : std_logic_vector(-1 to datawidth-1);
    
begin
	carry(-1) <= cin;
    cout <= carry(datawidth-1);
	-- instantiate a single-bit adder N times
    gen: for I in 0 to datawidth-1 generate
        add: adder port map(
                a => a(I),
                b => b(I),
                cin => carry(I - 1),
                s =>   sum(I),
                cout => carry(I));
   end generate;
end rtl;