freqdetect_top.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY freqdetect_top IS
	PORT(clk          	 		 : IN STD_LOGIC;   		--clk时钟
		 sign          	 		 : IN STD_LOGIC;		--待测信号
		 mode          	 		 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  --测量模式
		 q      				 : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);--测量结果数值输出
		 dp					     : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));--小数点
END freqdetect_top;
ARCHITECTURE rtl OF freqdetect_top IS
	--量程估计
	COMPONENT classify2
		PORT(clk : IN STD_LOGIC;						--全局时钟
			 sign : IN STD_LOGIC;       				--待测信号
			 class : OUT INTEGER RANGE 0 TO 7);   		--量程编号
	END COMPONENT;
	--计数时钟和闸门产生
	COMPONENT control
		PORT(clk : IN STD_LOGIC;
			 sign : IN STD_LOGIC;
			 class : IN INTEGER RANGE 0 TO 7;  			--量程编号
			 clk_out : OUT STD_LOGIC;   				--周期测量计数器时钟
			 gate   : OUT STD_LOGIC;
			 mode   : IN STD_LOGIC_VECTOR(1 DOWNTO 0));	--周期测量计数器闸门
	END COMPONENT;
	--周期测量计数器
	COMPONENT fine_detect
		PORT(clk : IN STD_LOGIC;         				                  
			 gate : IN STD_LOGIC;                          
			 q   : OUT STD_LOGIC_VECTOR(27 DOWNTO 0));	--计数结果输出
	END COMPONENT;	
	--除法器
	COMPONENT divider
		PORT(clk 		: IN STD_LOGIC;                           --计数时钟
			 divisor 	: IN STD_LOGIC_VECTOR(27 DOWNTO 0);       --除数
			quotient   	: OUT STD_LOGIC_VECTOR(27 DOWNTO 0));	  --除法器结果
	END COMPONENT;
    --小数点产生器
	COMPONENT radixpoint_gen
		PORT(class          	 : IN INTEGER RANGE 0 TO 7;           --量程编号
			 mode     			 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);   --测量模式
			 dp					 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --小数点控制
	END COMPONENT;
	--量程编号
	SIGNAL class  : INTEGER RANGE 0 TO 7;
	--周期测量计数器的时钟
	SIGNAL finedetect_clk  : STD_LOGIC;
	--周期测量计数器的计数闸门
	SIGNAL finedetect_gate : STD_LOGIC;	
	--测量结果的周期表示周期
	SIGNAL period          : STD_LOGIC_VECTOR(27 DOWNTO 0);
	--测量结果的频率表示
	SIGNAL frequence       : STD_LOGIC_VECTOR(27 DOWNTO 0);
BEGIN
	--量程估计
    classify: classify2 
	PORT MAP (clk => clk, 
	          sign => sign,
			  class => class);
	--周期测量计数器的时钟和闸门产生
	controler: control 
	PORT MAP (clk => clk, 
	          sign => sign,
			  class => class,
			  mode => mode,
                  clk_out => finedetect_clk,
			  gate => finedetect_gate);
	--周期测量计数器
	finedetect: fine_detect
	PORT MAP (clk => finedetect_clk,
			  gate => finedetect_gate,
			  q => period);
	--除法器
	divid : divider
	PORT MAP (clk => clk,
			  divisor => period,
			  quotient => frequence);
	--小数点产生模块
	radixpoint:radixpoint_gen
	PORT MAP( class => class,
			  mode => mode,
			  dp => dp);
	--多路选通器	
	PROCESS(mode,period,frequence)
	BEGIN
		CASE mode IS
			WHEN "00" => q <= period;
			WHEN "01" => q <= frequence;
			WHEN "10" => q <= period;
			WHEN OTHERS => q <= "0000000000000000000000000000";
		END CASE;
	END PROCESS;
END rtl;