mux3_8.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux3_8 is PORT(
        a, b, c, d,e,f,g,h:     IN  STD_LOGIC;							--输入8路。
        s:           			IN  STD_LOGIC_VECTOR(2 DOWNTO 0);	--地址信号
        z:           			OUT STD_LOGIC			--一路输出信号宽度为4
        );
END mux3_8;
ARCHITECTURE behavier OF mux3_8 IS
BEGIN
PROCESS (a, b, c, d, e, f, g, h, s)
   		BEGIN
                IF s = "000" THEN
                        z <= a; 
                ELSIF s = "001" THEN
                        z <= b;
                ELSIF s = "010" THEN
                        z <= c;
                ELSIF s = "011" THEN
                        z <= d;
				ELSIF s = "100" THEN
                        z <= e;
				ELSIF s = "101" THEN
                        z <= f;
				ELSIF s = "110" THEN
                        z <= g;
                ELSE
                        z <= h;
                END IF;
        END PROCESS;
END behavier;