and8.vhd

这是一些经典的vhdl example

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and8 IS
PORT(
		a1,a2,a3,a4,a5,a6,a7,a8		: IN	STD_LOGIC;
		y	    					: OUT	STD_LOGIC);
END and8;
ARCHITECTURE behavier OF and8 IS
BEGIN
	y<=a1 AND a2 AND a3 AND a4 AND a5 AND a6 AND a7 AND a8;
END behavier;