light.txt

梁祝乐曲演奏电路设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity light is
port(clk:in std_logic;
       q1:out std_logic_vector(5 downto 0));
end light;
architecture a of light is
signal t,q:std_logic;
signal a:std_logic_vector(5 downto 0);
begin
cnt:process(clk)
begin
if (clk'event and clk='1')then
   if (a=63)then a<="000001";t<=not t;
elsif t='1'then a<=a+1;
elsif t='0'and q='1'then
      a<=a+1;q<=not q;
elsif t='0'and q='0'then
      q<=not q;
end if;
end if;
end process;
q1<=a;
end a;