代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/326886/13111378
vhd a8255.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY a8255 IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR
www.eeworm.com/read/241759/13121739
vhd division.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity division is
generic(SIZE: INTEGER := 8);
port(reset: in STD_LOGI
www.eeworm.com/read/139799/13130493
vhd example7-6.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test3 IS
PORT (in1, in2, in3 : IN Std_Logic;
in4 : IN Std_Logic;
out1 : BUFFER Std_Logic);
END test3;
ARCHITECTURE example3 O
www.eeworm.com/read/139799/13130605
vhd example11-26.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE pak IS
PROCEDURE add (in1, in2 : IN Std_Logic_Vector;
carry_in : IN Std_Logic;
sum : OUT Std_Logic_Vector;
www.eeworm.com/read/139799/13130715
vhd example15-4.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
ENTITY ttest IS
END ttest;
ARCHITECTURE ttest OF ttest IS
COMPONENT detector
PORT(
d21_d:IN std_logic;
d21_c:IN std
www.eeworm.com/read/139799/13130790
vhd example10-4.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE WORK.pak.ALL;
ENTITY comparator IS
GENERIC (delay : TIME);
PORT (n, m : IN Std_Logic_Vector (1 DOWNTO 0);
ge, le, e, g, l : OUT Std_Log
www.eeworm.com/read/139799/13130850
vhd example14-4.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stack IS
PORT (
clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
push: IN STD_LOGIC;
pop: IN STD_LOGIC;
empty: OUT STD_LOGIC;
full: OUT
www.eeworm.com/read/139799/13130885
vhd example14-5.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
ENTITY th99cell IS
PORT(
PEbar:IN std_logic;
RSTbar:IN std_logic;
CSbar:IN std_logic;
clk:IN std_logic;
www.eeworm.com/read/326570/13134790
vhd musictop.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity musictop is
Port ( clk4Hz,clk28khz :in std_logic;
handTOauto
www.eeworm.com/read/139685/13139904
txt adder_variety_style.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------