example14-4.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY stack IS
	PORT (
		clk: IN STD_LOGIC;
		reset: IN STD_LOGIC;
		push: IN STD_LOGIC;
		pop: IN STD_LOGIC;
		empty: OUT STD_LOGIC;
		full: OUT STD_LOGIC;
		datain: IN STD_LOGIC_vector (7 downto 0);
		dataout: OUT STD_LOGIC_vector (7 downto 0)
		);
END stack;

ARCHITECTURE behave OF stack IS
	SIGNAL count: integer range 0 to 255;
	--function definition
	FUNCTION btologic ( din: IN boolean) RETURN std_logic IS
	BEGIN
		CASE din IS
			WHEN true=> RETURN '1';
			WHEN false=> RETURN '0';
		END CASE;
	END FUNCTION btologic;
BEGIN
	empty<=btologic(count=0);
	full<=btologic(count=255);
	main:PROCESS(clk)
		TYPE STACK_TYPE IS array (255 downto 0) OF std_logic_vector(7 downto 0);
		VARIABLE s:STACK_TYPE;
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF reset='1' THEN
				count<=0;
			ELSIF push='1' THEN
				s(255 downto 1):=s( 254 downto 0);
				s(0):=datain;
				count<=count+1;
			ELSIF pop='1' THEN
				dataout<=s(0);
				s(254 downto 0):=s(255 downto 1);
				count<=count-1;
			END IF;
		END IF;
	END PROCESS main;
END behave;