example12-5.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY dff IS
	PORT (
		clk: IN STD_LOGIC;
		data: IN STD_LOGIC;
		q: OUT STD_LOGIC
		);
END dff;

ARCHITECTURE behave OF dff IS
BEGIN
	PROCESS(clk,data)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			q<=data;
		END IF;
	END PROCESS;  
END behave;