example12-3.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY  latch3 IS
	PORT (
		reset: IN std_logic;
		clk: IN std_logic;
		load: IN std_logic;
		data: IN std_logic;
		q: OUT std_logic
		);
END latch3;


ARCHITECTURE behave OF latch3 IS
BEGIN
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF reset='1' THEN
				q<='0';
			ELSIF load='1' THEN
				q<=data;
			END IF;
		END IF;
	END PROCESS;
END behave;