example14-5.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY th99cell IS
	PORT(
		PEbar:IN std_logic;
		RSTbar:IN std_logic;
		CSbar:IN std_logic;
		clk:IN std_logic;
		din:IN std_logic_vector(7 downto 0);
		dout:OUT std_logic_vector(7 downto 0);
		DBUS:IN std_logic_vector(7 downto 0);
		ABUS:IN std_logic_vector(7 downto 0);
		ALE:IN std_logic;
		Rbar:IN std_logic;
		Wbar:IN std_logic;
		ap:OUT std_logic_vector(15 downto 0);
		d00:OUT std_logic_vector(6 downto 0);
		d01:OUT std_logic_vector(6 downto 0);
		d10:OUT std_logic_vector(6 downto 0);
		minute:OUT std_logic_vector(13 downto 0);
		hour:OUT std_logic_vector(13 downto 0)
		);
END  th99cell;

ARCHITECTURE behave OF th99cell IS
	COMPONENT controlLer
		PORT(
			PEbar:IN std_logic;
			CSbar:IN std_logic;
			RSTbar:IN std_logic;
			clk:IN std_logic;
			din:IN std_logic_vector(7 downto 0);
			dout:OUT std_logic_vector(7 downto 0);
			DBUS:IN std_logic_vector(7 downto 0);
			ABUS:IN std_logic_vector(7 downto 0);
			ALE:IN std_logic;
			Rbar:IN std_logic;
			Wbar:IN std_logic;
			number:OUT integer range 0 to 255;
			conminute:OUT std_logic_vector(7 downto 0);
			conhour:OUT std_logic_vector(7 downto 0)
			);
	END COMPONENT;
	
	COMPONENT compactor
		PORT(
			ap:OUT std_logic_vector(15 downto 0);
			RSTbar:IN std_logic;
			number:IN integer range 0 to 255
);
	END COMPONENT;
	
	COMPONENT templater
		PORT(
			number:IN integer range 0 to 255;
			RSTbar:IN std_logic;
			d00:OUT std_logic_vector(6 downto 0); 
			d01:OUT std_logic_vector(6 downto 0); 
			d10:OUT std_logic_vector(6 downto 0)
			);
	END COMPONENT;
	
	COMPONENT timer
		PORT(
			clk:IN std_logic;
			RSTbar:IN std_logic;
			conminute:IN std_logic_vector(7 downto 0);
			conhour:IN std_logic_vector(7 downto 0);
			minute:OUT std_logic_vector(13 downto 0); 
			hour:OUT std_logic_vector(13 downto 0) 
			);
	END COMPONENT;
	
	SIGNAL number:integer range 0 to 255;
	SIGNAL conminute:std_logic_vector(7 downto 0);
	SIGNAL conhour:std_logic_vector(7 downto 0);
	
BEGIN
	u1:controller
	PORT MAP(
		clk=>clk,
		DBUS=>DBUS,
		ABUS=>ABUS,
		ALE=>ALE,
		CSbar=>CSbar,
		Rbar=>Rbar,
		Wbar=>Wbar,
		din=>din,
		dout=>dout,
		PEbar=>PEbar,
		RSTbar=>RSTbar,
		number=>number,
		conminute=>conminute,
		conhour=>conhour
		);
	
	u2:compactor
	PORT MAP
(
		number=>number,
		RSTbar=>RSTbar,
		ap=>ap
		);
		
	u3:templater
	PORT MAP(
		number=>number,
		RSTbar=>RSTbar,
		d00=>d00,
		d01=>d01,
		d10=>d10
		);
	
	u4:timer
	PORT MAP(
		conminute=>conminute,
		conhour=>conhour,
		minute=>minute,
		hour=>hour,
		RSTbar=>RSTbar,
		clk=>clk
		);
	
END behave;

CONFIGURATION conth99cell OF th99cell IS
	FOR behave
		FOR u1:controller
			USE ENTITY work.controller(behave);
		END FOR;
		FOR u2:compactor
			USE ENTITY work.compactor(behave);
		END FOR;
		FOR u3:templater
			USE ENTITY work.templater(behave);
		END FOR;
		FOR u4:timer
			USE ENTITY work.timer(behave);
		END FOR;
	END FOR;
END conth99cell;