📄 musictop.vhd
字号:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity musictop is
Port ( clk4Hz,clk28khz :in std_logic;
handTOauto : in std_logic;
code1 :out std_logic_vector(6 downto 0);
index1 :in std_logic_vector(7 downto 0);
high1 :out std_logic;
spkout :out std_logic);
end musictop;
architecture Behavioral of musictop is
component automusic
Port ( clk :in std_logic;
Auto: in std_logic;
index2:in std_logic_vector(7 downto 0);
index0 : out std_logic_vector(7 downto 0));
end component;
component tone
Port ( index : in std_logic_vector(7 downto 0);
code : out std_logic_vector(6 downto 0);
high : out std_logic;
tone0 : out integer range 0 to 120);
end component;
component speaker
Port ( clk1 : in std_logic;
tone1 : in integer range 0 to 120;
spks : out std_logic);
end component;
signal tone2: integer range 0 to 120;
signal indx:std_logic_vector(7 downto 0);
begin
u0:automusic port
map(clk=>clk4HZ,index2=>index1,index0=>indx,Auto=>handtoAuto);
u1: tone port map(index=>indx,tone0=>tone2,code=>code1,high=>high1);
u2: speaker port map(clk1=>clk28kHZ,tone1=>tone2,spks=>spkout);
end Behavioral;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -