example15-4.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;

ENTITY ttest IS
END ttest;

ARCHITECTURE ttest OF ttest IS
	COMPONENT detector
		PORT(
			d21_d:IN std_logic;
			d21_c:IN std_logic;
			dbi:IN std_logic_vector(3 downto 0);
			out1:IN std_logic;
			r:IN std_logic;
			code_out:OUT std_logic_vector(0 to 7)
			);
	END COMPONENT;	
	COMPONENT fromfile
		PORT(
			d21_d:OUT std_logic;
			clock:IN std_logic
			);
	END COMPONENT;	
	SIGNAL d21_c : std_logic;
	SIGNAL d21_d : std_logic;
	SIGNAL dbi : std_logic_vector(3 downto 0);
	SIGNAL out1 : std_logic;
	SIGNAL r : std_logic;
	SIGNAL code_out:std_logic_vector(0 to 7);	
BEGIN	
	u1: detector 
	PORT MAP(
		d21_d=>d21_d,
		d21_c=>d21_c,
		dbi =>dbi,
		out1 =>out1,
		r =>r,
		code_out=>code_out
		);
	u2:fromfile
	PORT MAP(
		d21_d=>d21_d,
		clock=>d21_c
		);
	dbi<="1000";
	out1<='0','1' after 200 ns,'0' after 260 ns;
	r<='0','1' after 30 ns,'0' after 100 ns;
	PROCESS
	BEGIN
		d21_c<='0';
		WAIT FOR 10 ns;
		d21_c<='1';
		WAIT FOR 10 ns;
	END PROCESS;	
END ttest;
CONFIGURATION ctest OF ttest IS
	FOR ttest
		FOR u1:detector
			USE ENTITY work.detector(detector);
		END FOR;
		FOR u2:fromfile
			USE ENTITY work.fromfile(fromfile);
		END FOR;
	END FOR;
END ctest