example10-4.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE WORK.pak.ALL;
ENTITY comparator IS
  GENERIC (delay : TIME);
  PORT (n, m : IN Std_Logic_Vector (1 DOWNTO 0);
        ge, le, e, g, l : OUT Std_Logic);
END comparator;
ARCHITECTURE arc_3 OF comparator IS
BEGIN
  PROCESS (n, m)
    VARIABLE sel : Std_Logic_Vector (2 DOWNTO 0);
  BEGIN
	sel := n(1) & n(0) & m(1);
    CASE sel IS
      WHEN "000" =>
        ge <= NOT m (0) AFTER delay;
      le <= '1' AFTER delay;
        e <= NOT m (0) AFTER delay;
        g <= '0' AFTER delay;
      l <= m (0) AFTER delay;
      WHEN "001" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= m (0) AFTER delay;
      WHEN "010" =>
        ge <= '1' AFTER delay;
      le <= m (0) AFTER delay;
        e <= m (0) AFTER delay;
        g <= NOT m (0) AFTER delay;
      l <= '0' AFTER delay;
      WHEN "011" =>
        ge <= '0' AFTER delay;
      le <= '1' AFTER delay;
        e <= '0' AFTER delay;
        g <= '0' AFTER delay;
      l <= '1' AFTER delay;
      WHEN "100" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "101" =>
        ge <= NOT m (0) AFTER delay;
      le <= '1' AFTER delay;
        e <= NOT m (0) AFTER delay;
        g <= '0' AFTER delay;
      l <= m (0) AFTER delay;
      WHEN "110" =>
        ge <= '1' AFTER delay;
      le <= '0' AFTER delay;
        e <= '0' AFTER delay;
        g <= '1' AFTER delay;
      l <= '0' AFTER delay;
      WHEN "111" =>
        ge <= '1' AFTER delay;
      le <= m (0) AFTER delay;
        e <= m (0) AFTER delay;
        g <= NOT m (0) AFTER delay;
      l <= '0' AFTER delay;
	  WHEN OTHERS => NULL;
  END CASE;
  END PROCESS;
END arc_3;