代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/399945/7820572
vhd jtd0.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jtd0 is
port(clk: in std_logic;
reset: in std_logic;
--led7s: out std_
www.eeworm.com/read/399933/7821486
vhd jtd0.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jtd0 is
port(clk: in std_logic;
reset: in std_logic;
--led7s: out std_
www.eeworm.com/read/199789/7822576
vhd 加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
www.eeworm.com/read/199789/7822579
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/199789/7822637
vhd 相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
www.eeworm.com/read/299838/7828805
vhd mul2.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:40:44 04/07/08
-- Design Name:
-- Module Name: mul2 - B
www.eeworm.com/read/299488/7847262
vhd vgacore.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgacore is
Port ( clk : in std_logic;
reset : in std_logic;
www.eeworm.com/read/434686/7849349
vhd qpsk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity qpsk is
port(
ClkxCI : in std_logic;
ResetxRBI : in std_logic;
DataInxDI : in std_logic_vector
www.eeworm.com/read/399395/7866007
vhd decode1.vhd
-------------------------------------------------------------
--Copyright (C), 2004- , Huangwei. --
--File name:decode1(解码器) --
--Auth
www.eeworm.com/read/299231/7871682
vhd test.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity test is
port( reset, clk : in std_logic;
datin : in std_logic_vector( 9 downto 0 );
datout : out std_logic_v