代码搜索:std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
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h sort.h

#include using namespace std;
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h defs.h

#include using namespace std;
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h defs.h

#include using namespace std;
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h defs.h

#include using namespace std;
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vhd counter24.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity counter24 is port( clk,clr:in std_logic; cout:out std_logic; low,high:out st
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vhd circuit.vhd

LIBRARY ieee; USE ieee.std_logic_1164.all; USE IEEE.numeric_std.ALL; ENTITY circuit IS -- Declarations PORT( clk : IN std_logic; reset : IN std_logic; fmin : IN s
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vhd txmit_tb.vhd

-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_v
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vhd fenpin.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenpin is port(clk : in std_logic; clk1hz:out std_logic); end fenpin; architecture one of fenpin
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vhd dplay.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dplay is port(stop: in std_logic; clk: in std_logic; segin: in std_logi
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vhd traffic_lights.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity traffic_lights is port(clk: in std_logic;------1khz; stop:in std_logic; adr:out std_logic_vector(1