traffic_lights.vhd

vhdl的铜须等

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic_lights is
port(clk: in  std_logic;------1khz;
     stop:in  std_logic;
     adr:out  std_logic_vector(1 downto 0);
     seg:out  std_logic_vector(6 downto 0);
     snr,sng,sny:out std_logic;
     ewr,ewg,ewy:out std_logic);
end traffic_lights;
architecture rtl of traffic_lights is
component fenpin 
   port(clk:in std_logic;
        clk1hz:out std_logic);
end component;
component ctr 
  port(stop:  in  std_logic;
        clk: in std_logic;
       snr,sng,sny:out std_logic;
       ewr,ewg,ewy:out std_logic;
       one,ten:out std_logic_vector(3 downto 0));
end component;
component saomiao 
  port(clk: in  std_logic;  ----1khz;
       one,ten:in     std_logic_vector(3 downto 0);
       adr:out std_logic_vector(1 downto 0);
       data:out std_logic_vector(3 downto 0));
end component;
component display 
   port(data: in  std_logic_vector(3 downto 0);
        seg_t:out std_logic_vector(6 downto 0));
end component;
component dplay
   port(stop:          in  std_logic;
        clk:           in  std_logic;
        segin:         in  std_logic_vector(6 downto 0);
        r1_t,g1_t,y1_t:in  std_logic;
        r2_t,g2_t,y2_t:in  std_logic;
        snr,sng,sny:   out std_logic;
        ewr,ewg,ewy:   out std_logic;
        seg:           out std_logic_vector(6 downto 0));
end component;
signal temp1,temp2:std_logic_vector(6 downto 0);
signal clk1hz:std_logic;
signal one,ten:std_logic_vector(3 downto 0);
signal r1,g1,y1,r2,g2,y2:std_logic;
signal r_1,g_1,y_1,r_2,g_2,y_2:std_logic;
signal adr_temp:std_logic_vector(1 downto 0);
signal data:std_logic_vector(3 downto 0);
begin
  u0: fenpin  port map (clk,clk1hz);
  u1: ctr     port map (stop,clk1hz,r1,g1,y1,r2,g2,y2,one,ten);
  u2: saomiao port map (clk,one,ten,adr_temp,data);
  u3: display port map (data,temp1);
  u4: dplay   port map (stop,clk1hz,temp1,r1,g1,y1,r2,g2,y2,r_1,g_1,y_1,r_2,g_2,y_2,temp2);
  adr<=adr_temp;
  seg<=temp2;
  snr<=r_1;
  sng<=g_1;
  sny<=y_1;
  ewr<=r_2;
  ewg<=g_2;
  ewy<=y_2;
end rtl;