counter24.vhd

原创：基于VHDL语言编写的电子钟。采用模块化编写

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter24 is
port(
	clk,clr:in std_logic;
	cout:out std_logic;
	low,high:out std_logic_vector(3 downto 0)
);
end entity counter24;

architecture beh of counter24 is
signal l: integer range 0 to 9;
signal h: integer range 0 to 2;
begin
	process(clr,clk,l,h)
	begin
		if(clr='0')then
		l<=0;
		h<=0;
		cout<='0';
		elsif(clk 'event and clk='1')then
		if(h>=0 and h<2)then
			if(l>=0 and l<9)then
			l<=l+1;
			cout<='0';
			elsif(l=9)then
			l<=0;h<=h+1;
			cout<='0';
			end if;
		elsif(h=2)then
			if(l>=0 and l<3)then
			l<=l+1;cout<='0';
			elsif(l=3)then
			l<=0;h<=0;cout<='1';
			end if;
		end if;
		end if;
	end process;
low<=conv_std_logic_vector(l,4);
high<=conv_std_logic_vector(h,4);
end architecture beh ;