dplay.vhd

vhdl的铜须等

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dplay is
port(stop:          in  std_logic;
     clk:           in  std_logic;
     segin:         in  std_logic_vector(6 downto 0);
     r1_t,g1_t,y1_t:in  std_logic;
     r2_t,g2_t,y2_t:in  std_logic;
     snr,sng,sny:   out std_logic;
     ewr,ewg,ewy:   out std_logic;
     seg:           out std_logic_vector(6 downto 0));
end dplay;
architecture one of dplay is
begin
  process(stop,segin,r1_t,g1_t,y1_t,r2_t,g2_t,y2_t)
    begin
      if(stop='1')then
        snr<='1';
        ewr<='1';
        sng<='0';
        sny<='0';
        ewg<='0';
        ewy<='0';
        seg(0)<=segin(0)and clk;
        seg(1)<=segin(1)and clk;
        seg(2)<=segin(2)and clk;
        seg(3)<=segin(3)and clk;
        seg(4)<=segin(4)and clk;
        seg(5)<=segin(5)and clk;
        seg(6)<=segin(6)and clk;
      else
        snr<=r1_t;
        ewr<=g1_t;
        sng<=y1_t;
        sny<=r2_t;
        ewg<=g2_t;
        ewy<=y2_t;
        seg<=segin;
      end if;
  end process;
end one;