fenpin.vhd

vhdl的铜须等

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is        
port(clk : in std_logic;
     clk1hz:out std_logic);
end fenpin;
architecture one of fenpin is
signal q:std_logic;
begin
process(clk)
variable cnt: integer range 0 to 499;
begin
if(clk 'event and clk='1')then
   if(cnt=499)then
     q<=not q;
     cnt:=0;
   else
     cnt:=cnt+1;
   end if;
end if;
end process;
clk1hz<=q;
end one;