代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

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www.eeworm.com/read/298277/7968901

txt 说明.txt

0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。
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www.eeworm.com/read/316426/13522948

gfl sum.gfl

# XST (Creating Lso File) : sum.lso # xst flow : RunXST sum.syr sum.prj sum.sprj sum.ana sum.stx sum.cmd_log # XST (Creating Lso File) : sum.lso # xst flow : RunXST sum.syr sum.prj sum
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www.eeworm.com/read/314805/13558857

gfl mycpu16.gfl

# ProjNav -> New Source -> TBW e:\资料\计算机设计与实践\mycpu16\__projnav\hb_cmds # Bencher Waveform : PDCL (jhdparse) # ModelSim : Simulate Behavioral VHDL Model cpu_16_wave.fdo # ModelSim : Simulate Beha
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www.eeworm.com/read/309739/13665119

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# Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl # reading C:\Modeltech_6.0\win32/../modelsim.ini # reading modelsim.ini # // ModelSim SE 6.0 Aug 19 2004 # // # // Copyright Mentor Graphics Corpo
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www.eeworm.com/read/308751/13693659

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# Reading C:/Modeltech_5.6/tcl/vsim/pref.tcl # ** Error: Failure to license for viewer. # Unable to checkout a viewer lice# Model Technology ModelSim SE vlog 5.6 Compiler 2002.03 Mar 15 2002 # --
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www.eeworm.com/read/308751/13693716

gfl tst.gfl

# Project -> New Source -> CoreGen IP __projnav/coregenApp_tcl.rsp __projnav/coregen.rsp coregen.prj coregen.fin # Coregen : View Coregen Master Log fifo_asyn.coregen_log __projnav/xcoTOcoregen
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www.eeworm.com/read/303148/13820959

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# Reading D:/Modeltech_6.0/tcl/vsim/pref.tcl # // ModelSim SE 6.0 Aug 19 2004 # // # // Copyright Mentor Graphics Corporation 2004 # // All Rights Reserved. # // # // THIS WORK
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www.eeworm.com/read/493986/6386097

gfl importantversion.gfl

# XST (Creating Lso File) : fsm.lso # xst flow : RunXST fsm.syr fsm.prj fsm.sprj fsm.ana fsm.stx fsm.cmd_log fsm.ngc fsm.ngr # Implmentation : Translate __projnav/ngdbuild.err __projnav/
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www.eeworm.com/read/493331/6400902

vstf vish_stacktrace.vstf

# Current time Tue May 12 16:53:46 2009 # ModelSim Stack Trace # Program = vish # Id = "6.0" # Version = "2004.08" # Date = "Aug 19 2004" # Platform = win32 Exception c0000005 has occurred at
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www.eeworm.com/read/492763/6408721

mti uart.cr.mti

D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v {0 {vlog -work work -nocovercells D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v Model Technology ModelSim ALT
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