importantversion.gfl

VHDL source code for test machine.

# XST (Creating Lso File) : 
fsm.lso
# xst flow : RunXST
fsm.syr
fsm.prj
fsm.sprj
fsm.ana
fsm.stx
fsm.cmd_log
fsm.ngc
fsm.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\final15.06.07\project\importantversion/_ngo
fsm.ngd
fsm_ngdbuild.nav
fsm.bld
.untf
fsm.cmd_log
# Implmentation : Floorplan Design
__projnav/xlateFloorPlanner.rsp
# XST (Creating Lso File) : 
fsm.lso
# xst flow : RunXST
fsm.syr
fsm.prj
fsm.sprj
fsm.ana
fsm.stx
fsm.cmd_log
fsm.ngc
fsm.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\final15.06.07\project\importantversion/_ngo
fsm.ngd
fsm_ngdbuild.nav
fsm.bld
fsm.ucf.untf
fsm.cmd_log
# XST (Creating Lso File) : 
fsm.lso
# xst flow : RunXST
fsm.syr
fsm.prj
fsm.sprj
fsm.ana
fsm.stx
fsm.cmd_log
fsm.ngc
fsm.ngr
# ProjNav -> New Source -> TBW
D:\CShT\Final15.06.07\Project\ImportantVersion\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\final15.06.07\project\importantversion/_ngo
fsm.ngd
fsm_ngdbuild.nav
fsm.bld
fsm.ucf.untf
fsm.cmd_log
# Implementation : Map
fsm_map.ncd
fsm.ngm
fsm.pcf
fsm.nc1
fsm.mrp
fsm_map.mrp
fsm.mdf
__projnav/map.log
fsm.cmd_log
MAP_NO_GUIDE_FILE_CPF "fsm"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fsm.twr
fsm.twx
fsm.tsi
fsm.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fsm.ncd
fsm.par
fsm.pad
fsm_pad.txt
fsm_pad.csv
fsm.pad_txt
fsm.dly
reportgen.log
fsm.xpi
fsm.grf
fsm.itr
fsm_last_par.ncd
__projnav/par.log
fsm.placed_ncd_tracker
fsm.routed_ncd_tracker
fsm.cmd_log
PAR_NO_GUIDE_FILE_CPF "fsm"
# Implementation : Generate Post-Par Simulation Model
fsm_timesim.vhd
fsm_timesim.sdf
fsm_timesim.sdf
fsm_timesim.vhd
fsm_timesim.nlf
fsm.par_nlf
fsm.vhdsim_par
fsm.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test1.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Generate Expected Simulation Results
test1.ado
test1.ano
# XST (Creating Lso File) : 
indicator.lso
# xst flow : RunXST
indicator.syr
indicator.prj
indicator.sprj
indicator.ana
indicator.stx
indicator.cmd_log
indicator.ngc
indicator.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\final15.06.07\project\importantversion/_ngo
indicator.ngd
indicator_ngdbuild.nav
indicator.bld
.untf
indicator.cmd_log
# Implementation : Map
indicator_map.ncd
indicator.ngm
indicator.pcf
indicator.nc1
indicator.mrp
indicator_map.mrp
indicator.mdf
__projnav/map.log
indicator.cmd_log
MAP_NO_GUIDE_FILE_CPF "indicator"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
indicator.twr
indicator.twx
indicator.tsi
indicator.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
indicator.ncd
indicator.par
indicator.pad
indicator_pad.txt
indicator_pad.csv
indicator.pad_txt
indicator.dly
reportgen.log
indicator.xpi
indicator.grf
indicator.itr
indicator_last_par.ncd
__projnav/par.log
indicator.placed_ncd_tracker
indicator.routed_ncd_tracker
indicator.cmd_log
PAR_NO_GUIDE_FILE_CPF "indicator"
# XST (Creating Lso File) : 
project.lso
# xst flow : RunXST
project.syr
project.prj
project.sprj
project.ana
project.stx
project.cmd_log
project.ngc
project.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\final15.06.07\project\importantversion/_ngo
project.ngd
project_ngdbuild.nav
project.bld
.untf
project.cmd_log
# Implementation : Map
project_map.ncd
project.ngm
project.pcf
project.nc1
project.mrp
project_map.mrp
project.mdf
__projnav/map.log
project.cmd_log
MAP_NO_GUIDE_FILE_CPF "project"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
project.twr
project.twx
project.tsi
project.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
project.ncd
project.par
project.pad
project_pad.txt
project_pad.csv
project.pad_txt
project.dly
reportgen.log
project.xpi
project.grf
project.itr
project_last_par.ncd
__projnav/par.log
project.placed_ncd_tracker
project.routed_ncd_tracker
project.cmd_log
PAR_NO_GUIDE_FILE_CPF "project"
# XST (Creating Lso File) : 
testmachine.lso
# xst flow : RunXST
testmachine.syr
testmachine.prj
testmachine.sprj
testmachine.ana
testmachine.stx
testmachine.cmd_log
testmachine.ngc
testmachine.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\csht\final15.06.07\project\importantversion/_ngo
testmachine.ngd
testmachine_ngdbuild.nav
testmachine.bld
.untf
testmachine.cmd_log
# Implementation : Map
testmachine_map.ncd
testmachine.ngm
testmachine.pcf
testmachine.nc1
testmachine.mrp
testmachine_map.mrp
testmachine.mdf
__projnav/map.log
testmachine.cmd_log
MAP_NO_GUIDE_FILE_CPF "testmachine"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
testmachine.twr
testmachine.twx
testmachine.tsi
testmachine.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
testmachine.ncd
testmachine.par
testmachine.pad
testmachine_pad.txt
testmachine_pad.csv
testmachine.pad_txt
testmachine.dly
reportgen.log
testmachine.xpi
testmachine.grf
testmachine.itr
testmachine_last_par.ncd
__projnav/par.log
testmachine.placed_ncd_tracker
testmachine.routed_ncd_tracker
testmachine.cmd_log
PAR_NO_GUIDE_FILE_CPF "testmachine"
# ProjNav -> New Source -> TBW
D:\CShT\Final15.06.07\Project\ImportantVersion\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Implementation : Generate Post-Par Simulation Model
testmachine_timesim.vhd
testmachine_timesim.sdf
testmachine_timesim.sdf
testmachine_timesim.vhd
testmachine_timesim.nlf
testmachine.par_nlf
testmachine.vhdsim_par
testmachine.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
test_machine1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test_machine1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Implementation : Generate Post-Par Simulation Model
project_timesim.vhd
project_timesim.sdf
project_timesim.sdf
project_timesim.vhd
project_timesim.nlf
project.par_nlf
project.vhdsim_par
project.cmd_log
__projnav/netgen_par_tcl.rsp
# Simulation :Simulate Post-Place & Route VHDL Model
testProject.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
testProject.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
testMachine1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
testMachine1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
D:\CShT\Final15.06.07\Project\ImportantVersion\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
opit1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
opit1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
opit1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
opit1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
opit1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
opit1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
D:\CShT\Final15.06.07\Project\ImportantVersion\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
D:\CShT\Final15.06.07\Project\ImportantVersion\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
opit2.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
opit2.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
D:\CShT\Final15.06.07\Project\ImportantVersion\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Implementation : Generate Post-Map Simulation Model
fsm_map.vhd
fsm_map.sdf
fsm_map.sdf
fsm_map.vhd
fsm_map.nlf
fsm.map_nlf
fsm.vhdsim_map
fsm.cmd_log
__projnav/netgen_map_tcl.rsp
# Simulation :Simulate Post-Map VHDL Model
test1.map_vhw
_remap.tmp
__projnav/mtb.rsp
# ModelSim : Simulate Post-Map VHDL Model
test1.mdo
# ModelSim : Simulate Post-Map VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test1.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test1.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ProjNav -> New Source -> TBW
D:\CShT\Final15.06.07\Project\ImportantVersion\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test2.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test2.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test2.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test2.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Simulation :Simulate Post-Place & Route VHDL Model
test2.timesim_vhw
_remap.tmp
__projnav/ptb.rsp
# ModelSim : Simulate Post-Place & Route VHDL Model
test2.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Assign Package Pins Post-Translate
__projnav/xlatePace.rsp