transcript

Verilog编程

# Reading C:/Modeltech_5.6/tcl/vsim/pref.tcl 
# ** Error: Failure to license for viewer.
# Unable to checkout a viewer lice# Model Technology ModelSim SE vlog 5.6 Compiler 2002.03 Mar 15 2002
# -- Compiling module counter
# 
# Top level modules:
# 	counter
# Model Technology ModelSim SE vlog 5.6 Compiler 2002.03 Mar 15 2002
# -- Compiling module rom1
# 
# Top level modules:
# 	rom1
# Model Technology ModelSim SE vlog 5.6 Compiler 2002.03 Mar 15 2002
# -- Compiling module DDS1
# 
# Top level modules:
# 	DDS1
# Model Technology ModelSim SE vlog 5.6 Compiler 2002.03 Mar 15 2002
# -- Compiling module dds_tbw
# 
# Top level modules:
# 	dds_tbw
# Model Technology ModelSim SE vlog 5.6 Compiler 2002.03 Mar 15 2002
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps dds_tbw glbl 
# Loading work.dds_tbw
# Loading work.DDS1
# Loading work.counter
# ** Warning: (vsim-3009) [TSCALE] - Module 'counter' does not have a `timescale directive in effect, but previous modules do.
#         Region: /dds_tbw/UUT/counterclk
# Loading work.rom1
# ** Warning: (vsim-3009) [TSCALE] - Module 'rom1' does not have a `timescale directive in effect, but previous modules do.
#         Region: /dds_tbw/UUT/rom
# Loading C:\Modeltech_5.6\examples\Xilinxcorelib_ver.BLKMEMSP_V5_0
# Loading work.glbl
# ** Warning: (vsim-3015) DDS1.v(106): [PCDPC] - Port size does not match connection size (port 'addr').
#         Region: /dds_tbw/UUT/rom
# .wave
# ** Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use.
# File in use by: 丁??  Hostname: DWS  ProcessID: 4056
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf.  Using C:\DOCUME~1\ADMINI~1.ICB\LOCALS~1\Temp\wlft4.wlf instead.
# .structure
# .signals
# Invalid Address Warning #4: Warning in dds_tbw.UUT.rom.inst at time                 5000: Block memory address    x (xxxxxxxxxx) invalid. Valid depth configured as 0 to        1023
# No errors or warnings
# Break at dds_tbw.tfw line 113
# Simulation Breakpoint: Break at dds_tbw.tfw line 113
# MACRO ./dds_tbw.fdo PAUSED at line 16
destroy .wave
destroy .signals
destroy .structure