uart.cr.mti

基于verilog hdl的UART串口发送子程序。

D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v {0 {vlog -work work -nocovercells D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module TEST
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(21): near "[": syntax error, unexpected '['
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(23): near "=": Syntax error.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(25): near ";": Syntax error.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(26): near "=": Syntax error.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(27): near "=": Syntax error.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(28): near "=": Syntax error.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(48): near "++": Operator only allowed in SystemVerilog.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(57): near "++": Operator only allowed in SystemVerilog.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(70): Undefined variable: results.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(71): near "++": Operator only allowed in SystemVerilog.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(77): near "++": Operator only allowed in SystemVerilog.
** Error: D:/altera/90/modelsim_ae/examples/verilog/pli/fibonacci/fibonacci.v(78): BEGIN - END required around task/function statements

} {4.0 16.0} {}} {F:/My   Project/Verilog HDL/UART/uart_txd/export/uart_txd.v} {1 {vlog -work work -nocovercells {F:/My   Project/Verilog HDL/UART/uart_txd/export/uart_txd.v}
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module uart_txd_vlg_sample_tst
-- Compiling module uart_txd_vlg_check_tst
-- Compiling module uart_txd_vlg_vec_tst

Top level modules:
	uart_txd_vlg_vec_tst

} {} {}}