sum.gfl

这是一个用VHDL写的简易的CPU的程序

# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# ProjNav -> New Source -> TBW
e:\sum\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
fin.vhw
fin.ano
fin.tfw
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
sum.ngc
sum.ngr
# XST (Creating Lso File) : 
ieu.lso
# xst flow : RunXST
ieu.syr
ieu.prj
ieu.sprj
ieu.ana
ieu.stx
ieu.cmd_log
ieu.ngc
ieu.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# ModelSim : Simulate Behavioral VHDL Model
fin.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\sum/_ngo
sum.ngd
sum_ngdbuild.nav
sum.bld
sum.ucf.untf
sum.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\sum/_ngo
sum.ngd
sum_ngdbuild.nav
sum.bld
sum.ucf.untf
sum.cmd_log
# Implementation : Map
sum_map.ncd
sum.ngm
sum.pcf
sum.nc1
sum.mrp
sum_map.mrp
sum.mdf
__projnav/map.log
sum.cmd_log
MAP_NO_GUIDE_FILE_CPF "sum"
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\sum/_ngo
sum.ngd
sum_ngdbuild.nav
sum.bld
sum.ucf.untf
sum.cmd_log
# Implementation : Map
sum_map.ncd
sum.ngm
sum.pcf
sum.nc1
sum.mrp
sum_map.mrp
sum.mdf
__projnav/map.log
sum.cmd_log
MAP_NO_GUIDE_FILE_CPF "sum"
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\sum/_ngo
sum.ngd
sum_ngdbuild.nav
sum.bld
sum.ucf.untf
sum.cmd_log
# Implementation : Map
sum_map.ncd
sum.ngm
sum.pcf
sum.nc1
sum.mrp
sum_map.mrp
sum.mdf
__projnav/map.log
sum.cmd_log
MAP_NO_GUIDE_FILE_CPF "sum"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
sum.twr
sum.twx
sum.tsi
sum.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
sum.ncd
sum.par
sum.pad
sum_pad.txt
sum_pad.csv
sum.pad_txt
sum.dly
reportgen.log
sum.xpi
sum.grf
sum.itr
sum_last_par.ncd
__projnav/par.log
sum.placed_ncd_tracker
sum.routed_ncd_tracker
sum.cmd_log
PAR_NO_GUIDE_FILE_CPF "sum"
# Generate Programming File
__projnav/sum_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
sum.ut
# Generate Programming File
sum.bgn
sum.rbt
sum.ll
sum.msk
sum.drc
sum.nky
sum.bit
sum.bin
sum.isc
sum.cmd_log
# Edit Constraints (Text)
__projnav/parentEditConstraintsTextApp_tcl.rsp
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\sum/_ngo
sum.ngd
sum_ngdbuild.nav
sum.bld
sum.ucf.untf
sum.cmd_log
# Implementation : Map
sum_map.ncd
sum.ngm
sum.pcf
sum.nc1
sum.mrp
sum_map.mrp
sum.mdf
__projnav/map.log
sum.cmd_log
MAP_NO_GUIDE_FILE_CPF "sum"
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\sum/_ngo
sum.ngd
sum_ngdbuild.nav
sum.bld
sum.ucf.untf
sum.cmd_log
# Implementation : Map
sum_map.ncd
sum.ngm
sum.pcf
sum.nc1
sum.mrp
sum_map.mrp
sum.mdf
__projnav/map.log
sum.cmd_log
MAP_NO_GUIDE_FILE_CPF "sum"
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\sum/_ngo
sum.ngd
sum_ngdbuild.nav
sum.bld
sum.ucf.untf
sum.cmd_log
# Implementation : Map
sum_map.ncd
sum.ngm
sum.pcf
sum.nc1
sum.mrp
sum_map.mrp
sum.mdf
__projnav/map.log
sum.cmd_log
MAP_NO_GUIDE_FILE_CPF "sum"
# XST (Creating Lso File) : 
sum.lso
# xst flow : RunXST
sum.syr
sum.prj
sum.sprj
sum.ana
sum.stx
sum.cmd_log
ieu.ngc
sum.ngc
ieu.ngr
sum.ngr
# Implmentation : Translate