tst.gfl

Verilog编程

# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Coregen : View Coregen Master Log
fifo_asyn.coregen_log
__projnav/xcoTOcoregen_log_tcl.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XAW : PDCL (jhdparse)
__projnav/my_dcm1_jhdparse_tcl.rsp
# XAW : View HDL Source (Verilog)
my_dcm1.v
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
top.ngr
# View RTL Schematic
top.ngr
# XST (Creating Lso File) : 
dds4.lso
# xst flow : RunXST
dds4.syr
dds4.prj
dds4.sprj
dds4.ana
dds4.stx
dds4.cmd_log
dds4.ngr
# View RTL Schematic
dds4.ngr
# XST (Creating Lso File) : 
DDS1.lso
# xst flow : RunXST
DDS1.syr
DDS1.prj
DDS1.sprj
DDS1.ana
DDS1.stx
DDS1.cmd_log
DDS1.ngr
# View RTL Schematic
DDS1.ngr
# View RTL Schematic
DDS1.ngr
# XST (Creating Lso File) : 
tst.lso
# Check Syntax
tst.stx
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
tst.lso
# Check Syntax
tst.stx
# XST (Creating Lso File) : 
tst.lso
# Check Syntax
tst.stx
# XST (Creating Lso File) : 
tst.lso
# Check Syntax
tst.stx
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# View RTL Schematic
tst.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
tst.lso
# Check Syntax
tst.stx
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# View RTL Schematic
tst.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
tst.lso
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
tst.lso
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngr
# View RTL Schematic
tst.ngr
# XST (Creating Lso File) : 
top.lso
# Check Syntax
top.stx
top.ngc
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
DDS1.ngr
dds4.ngr
top.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
DDS1.ngr
dds4.ngr
top.ngr
# ProjNav -> New Source -> TBW
E:\ise6.1\tst\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
top_tbw.vhw
top_tbw.ano
top_tbw.tfw
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
top_tbw.vhw
top_tbw.ano
top_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
top_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ProjNav -> New Source -> TBW
E:\ise6.1\tst\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
dds_tbw.vhw
dds_tbw.ano
dds_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
dds_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ProjNav -> New Source -> TBW
E:\ise6.1\tst\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
counter_tbw.vhw
counter_tbw.ano
counter_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
counter_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
DDS1.lso
# xst flow : RunXST
DDS1.syr
DDS1.prj
DDS1.sprj
DDS1.ana
DDS1.stx
DDS1.cmd_log
DDS1.ngc
DDS1.ngr
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
DDS1.lso
# xst flow : RunXST
DDS1.syr
DDS1.prj
DDS1.sprj
DDS1.ana
DDS1.stx
DDS1.cmd_log
DDS1.ngc
DDS1.ngr
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
dds_tbw.vhw
dds_tbw.ano
dds_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
dds_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
top_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
top_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
top_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
top_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
top_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\ise6.1\tst\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ding_tbw.vhw
ding_tbw.ano
ding_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
ding_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
armtst.lso
# xst flow : RunXST
armtst.syr
armtst.prj
armtst.sprj
armtst.ana
armtst.stx
armtst.cmd_log
armtst.ngc
armtst.ngr
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\ise6.1\tst\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
armtst_tbw.vhw
armtst_tbw.ano
armtst_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
armtst_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
armtst_tbw.vhw
armtst_tbw.ano
armtst_tbw.tfw
# ModelSim : Simulate Behavioral Verilog Model
armtst_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
armtst_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
armtst_tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# ProjNav -> New Source -> TBW
E:\ise6.1\tst\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
arm.vhw
arm.ano
arm.tfw
# ModelSim : Simulate Behavioral Verilog Model
arm.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
armtst.lso
# xst flow : RunXST
armtst.syr
armtst.prj
armtst.sprj
armtst.ana
armtst.stx
armtst.cmd_log
armtst.ngc
armtst.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\ise6.1\tst/_ngo
armtst.ngd
armtst_ngdbuild.nav
armtst.bld
armtst_ucf.ucf.untf
armtst.cmd_log
# XST (Creating Lso File) : 
armtst.lso
# xst flow : RunXST
armtst.syr
armtst.prj
armtst.sprj
armtst.ana
armtst.stx
armtst.cmd_log
armtst.ngc
armtst.ngr
# XST (Creating Lso File) : 
armtst.lso
# xst flow : RunXST
armtst.syr
armtst.prj
armtst.sprj
armtst.ana
armtst.stx
armtst.cmd_log
armtst.ngc
armtst.ngr
# xst flow : RunXST
tst.syr
tst.prj
tst.sprj
tst.ana
tst.stx
tst.cmd_log
tst.ngc
tst.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\ise6.1\tst/_ngo
tst.ngd
tst_ngdbuild.nav
tst.bld
.untf
tst.cmd_log
# Implementation : Map
tst_map.ncd
tst.ngm
tst.pcf
tst.nc1
tst.mrp
tst_map.mrp
tst.mdf
__projnav/map.log
tst.cmd_log
MAP_NO_GUIDE_FILE_CPF "tst"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
tst.twr
tst.twx
tst.tsi
tst.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
tst.ncd
tst.par
tst.pad
tst_pad.txt
tst_pad.csv
tst.pad_txt
tst.dly
reportgen.log
tst.xpi
tst.grf
tst.itr
tst_last_par.ncd
__projnav/par.log
tst.placed_ncd_tracker
tst.routed_ncd_tracker
tst.cmd_log
PAR_NO_GUIDE_FILE_CPF "tst"
# Generate Programming File
__projnav/tst_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
tst.ut
# Generate Programming File
tst.bgn
tst.rbt
tst.ll
tst.msk
tst.drc
tst.nky
tst.bit
tst.bin
tst.isc
tst.cmd_log
# Generate PROM, ACE, or JTAG File
tst.ace
xilinx.sys
tst.mpm
tst.mcs
tst.prm
tst.dst
tst.exo
tst.tek
tst.hex
tst.svf
tst.stapl
impact.cmd
_impact.log
_impact.cmd
# Generate PROM, ACE, or JTAG File
tst.ace
xilinx.sys
tst.mpm
tst.mcs
tst.prm
tst.dst
tst.exo
tst.tek
tst.hex
tst.svf
tst.stapl
impact.cmd
_impact.log
_impact.cmd
# Generate PROM, ACE, or JTAG File
tst.ace
xilinx.sys
tst.mpm
tst.mcs
tst.prm
tst.dst
tst.exo
tst.tek
tst.hex
tst.svf
tst.stapl
impact.cmd
_impact.log
_impact.cmd
# Generate PROM, ACE, or JTAG File
tst.ace
xilinx.sys
tst.mpm
tst.mcs
tst.prm
tst.dst
tst.exo
tst.tek
tst.hex
tst.svf
tst.stapl
impact.cmd
_impact.log
_impact.cmd
# Generate PROM, ACE, or JTAG File
tst.ace
xilinx.sys
tst.mpm
tst.mcs
tst.prm
tst.dst
tst.exo
tst.tek
tst.hex
tst.svf
tst.stapl
impact.cmd
_impact.log
_impact.cmd
# Configure Device (iMPACT)
tst.prm
tst.isc
tst.svf
xilinx.sys
tst.mcs
tst.exo
tst.hex
tst.tek
tst.dst
tst.dst_compressed
tst.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
tst.prm
tst.isc
tst.svf
xilinx.sys
tst.mcs
tst.exo
tst.hex
tst.tek
tst.dst
tst.dst_compressed
tst.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
tst.prm
tst.isc
tst.svf
xilinx.sys
tst.mcs
tst.exo
tst.hex
tst.tek
tst.dst
tst.dst_compressed
tst.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
tst.prm
tst.isc
tst.svf
xilinx.sys