代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/355654/10251377

mti test.cr.mti

D:/8051/i8051_dec.vhd {1 {vcom -work work -2002 -explicit -vopt D:/8051/i8051_dec.vhd Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006 -- Loading package standard -- Loading pack
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www.eeworm.com/read/297709/8002139

dmp test_i2c_to_gpio.dmp

$date Tue Nov 20 11:26:44 2007 $end $version ModelSim Version 6.1g $end $timescale 10ns $end $scope module test_I2C_to_GPIO $end $var parameter 0 ! tdelay $end $var parameter 0 " testcyc
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www.eeworm.com/read/306761/13738109

mti mips.cr.mti

F:/mips3/regfile.vhd {1 {vcom -work work -2002 -explicit -vopt F:/mips3/regfile.vhd Model Technology ModelSim SE vcom 6.2e Compiler 2006.11 Nov 16 2006 -- Loading package standard -- Loading packag
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www.eeworm.com/read/492763/6408714

transcript

# Reading D:/altera/90/modelsim_ae/tcl/vsim/pref.tcl # OpenFile {F:/My Project/Verilog HDL/UART/uart_txd/uart.mpf} # Loading project uart vsim -voptargs=+acc work.uart_txd_vlg_check_tst # vsim
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www.eeworm.com/read/492009/6429778

vcd stopwatch.vcd

$date Thu Mar 11 14:01:36 2004 $end $version ModelSim Version 5.8b $end $timescale 1ps $end $scope module testbench $end $scope module UUT $end $var wire 1 ! RESET $end $var wire 1 " STRTSTOP $end
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www.eeworm.com/read/408799/11369629

vcd stopwatch.vcd

$date Thu Mar 11 14:01:36 2004 $end $version ModelSim Version 5.8b $end $timescale 1ps $end $scope module testbench $end $scope module UUT $end $var wire 1 ! RESET $end $var wire 1 " STRTSTOP $end
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www.eeworm.com/read/228928/14357670

mti s_to_p.cr.mti

D:/research/Hardware/stop/s_to_p_tb.v {1 {vlog -work work D:/research/Hardware/stop/s_to_p_tb.v Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004 -- Compiling module s_to_p_tb To
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www.eeworm.com/read/224873/14565305

mti fifo.cr.mti

D:/HDLDesign/Lab1/FSM_tb.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab1/FSM_tb.vhd Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004 -- Loading package standard -- Loadi
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www.eeworm.com/read/18434/788233

vcd myvcdfile.vcd

$date Sun Nov 10 15:28:00 2002 $end $version ModelSim Version 5.5f $end $timescale 1ns $end $scope module test_counter $end $scope module dut $end $var parameter 32 ! tpd_clk_to_count $e
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www.eeworm.com/read/18434/789428

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# Compile of pll_ram.vo was successful. # Compile of pll_ram_tb.v was successful. # 2 compiles, 0 failed with no errors. vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/alte
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