fifo.cr.mti

FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合

D:/HDLDesign/Lab1/FSM_tb.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab1/FSM_tb.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fsm_tb
-- Compiling architecture behavial of fsm_tb

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/FIFOBuffer.vhd} {1 {vcom -work work -2002 -explicit {E:/miodelsim assign/FIFO-DC/Lab1/FIFOBuffer.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fifobuffer
-- Compiling architecture behav of fifobuffer

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/syn_tb.vhd} {1 {vcom -work work -2002 -explicit {E:/miodelsim assign/FIFO-DC/Lab1/syn_tb.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity syn_tb
-- Compiling architecture behavial of syn_tb

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/reader_fsm.vhd} {1 {vcom -work work -2002 -explicit {E:/miodelsim assign/FIFO-DC/Lab1/reader_fsm.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity reader_fsm
-- Compiling architecture behav of reader_fsm

} {} {}} D:/HDLDesign/Lab1/FIFOBuffer.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab1/FIFOBuffer.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fifobuffer
-- Compiling architecture behav of fifobuffer

} {} {}} D:/HDLDesign/Lab1/syn_tb.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab1/syn_tb.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity syn_tb
-- Compiling architecture behavial of syn_tb

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/writer_fsm.vhd} {1 {vcom -work work -2002 -explicit {E:/miodelsim assign/FIFO-DC/Lab1/writer_fsm.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity writer_fsm
-- Compiling architecture behav of writer_fsm

} {} {}} D:/HDLDesign/Lab1/reader_fsm.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab1/reader_fsm.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity reader_fsm
-- Compiling architecture behav of reader_fsm

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/reader_pointer.vhd} {1 {vcom -work work -2002 -explicit {E:/miodelsim assign/FIFO-DC/Lab1/reader_pointer.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Compiling entity reader_pointer
-- Compiling architecture behav of reader_pointer

} {} {}} D:/HDLDesign/Lab1/writer_fsm.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab1/writer_fsm.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity writer_fsm
-- Compiling architecture behav of writer_fsm

} {} {}} D:/HDLDesign/Lab1/reader_pointer.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab1/reader_pointer.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Compiling entity reader_pointer
-- Compiling architecture behav of reader_pointer

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/writer_pointer.vhd} {1 {vcom -work work -2002 -explicit -check_synthesis {E:/miodelsim assign/FIFO-DC/Lab1/writer_pointer.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Compiling entity writer_pointer
-- Compiling architecture behav of writer_pointer

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/pointer_tb.vhd} {1 {vcom -work work -2002 -explicit -check_synthesis {E:/miodelsim assign/FIFO-DC/Lab1/pointer_tb.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity pointer_tb
-- Compiling architecture behavial of pointer_tb

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/synchronizer.vhd} {1 {vcom -work work -2002 -explicit {E:/miodelsim assign/FIFO-DC/Lab1/synchronizer.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity synchronizer
-- Compiling architecture behav of synchronizer

} {} {}} D:/HDLDesign/Lab1/writer_pointer.vhd {1 {vcom -work work -2002 -explicit -check_synthesis D:/HDLDesign/Lab1/writer_pointer.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_std
-- Compiling entity writer_pointer
-- Compiling architecture behav of writer_pointer

} {} {}} D:/HDLDesign/Lab1/pointer_tb.vhd {1 {vcom -work work -2002 -explicit -check_synthesis D:/HDLDesign/Lab1/pointer_tb.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity pointer_tb
-- Compiling architecture behavial of pointer_tb

} {} {}} {E:/miodelsim assign/FIFO-DC/Lab1/FSM_tb.vhd} {1 {vcom -work work -2002 -explicit {E:/miodelsim assign/FIFO-DC/Lab1/FSM_tb.vhd}
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fsm_tb
-- Compiling architecture behavial of fsm_tb

} {} {}}