transcript

一本老师推荐的经典的VHDL覆盖基础的入门书籍

# Compile of pll_ram.vo was successful.
# Compile of pll_ram_tb.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb
# vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb 
# Loading work.pll_ram_tb
# Loading work.pll_ram
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(160): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(197): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(237): Instantiation of 'stratix_pll' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(385): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(431): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(469): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(509): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(549): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(587): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(625): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(661): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(690): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(727): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(764): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(801): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(838): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(875): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(912): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(956): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(985): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1022): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1059): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1096): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1133): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1170): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1207): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1246): Instantiation of 'stratix_ram_block' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1304): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1341): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1378): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1415): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work