stopwatch.vcd

watchdog with verilog

$date
	Thu Mar 11 14:01:36 2004
$end
$version
	ModelSim Version 5.8b
$end
$timescale
	1ps
$end
$scope module testbench $end
$scope module UUT $end
$var wire 1 ! RESET $end
$var wire 1 " STRTSTOP $end
$var wire 1 # CLK $end
$var wire 1 $ TENSOUT [6] $end
$var wire 1 % TENSOUT [5] $end
$var wire 1 & TENSOUT [4] $end
$var wire 1 ' TENSOUT [3] $end
$var wire 1 ( TENSOUT [2] $end
$var wire 1 ) TENSOUT [1] $end
$var wire 1 * TENSOUT [0] $end
$var wire 1 + ONESOUT [6] $end
$var wire 1 , ONESOUT [5] $end
$var wire 1 - ONESOUT [4] $end
$var wire 1 . ONESOUT [3] $end
$var wire 1 / ONESOUT [2] $end
$var wire 1 0 ONESOUT [1] $end
$var wire 1 1 ONESOUT [0] $end
$var wire 1 2 TENTHSOUT [9] $end
$var wire 1 3 TENTHSOUT [8] $end
$var wire 1 4 TENTHSOUT [7] $end
$var wire 1 5 TENTHSOUT [6] $end
$var wire 1 6 TENTHSOUT [5] $end
$var wire 1 7 TENTHSOUT [4] $end
$var wire 1 8 TENTHSOUT [3] $end
$var wire 1 9 TENTHSOUT [2] $end
$var wire 1 : TENTHSOUT [1] $end
$var wire 1 ; TENTHSOUT [0] $end
$var wire 1 < MACHINE_current_state_FFd3 $end
$var wire 1 = clk_dcm $end
$var wire 1 > MACHINE_current_state_FFd6 $end
$var wire 1 ? xcounter/N5 $end
$var wire 1 @ xcounter/N4 $end
$var wire 1 A xcounter/N3 $end
$var wire 1 B xcounter/N2 $end
$var wire 1 C xcounter/N6 $end
$var wire 1 D xcounter/N58 $end
$var wire 1 E xcounter/N7 $end
$var wire 1 F xcounter/N106 $end
$var wire 1 G xcounter/N119 $end
$var wire 1 H xcounter/N122 $end
$var wire 1 I xcounter/N132 $end
$var wire 1 J xcounter/N165 $end
$var wire 1 K xcounter/N182 $end
$var wire 1 L xcounter/N199 $end
$var wire 1 M xcounter/N216 $end
$var wire 1 N xtermcnt $end
$var wire 1 O GLOBAL_LOGIC0 $end
$var wire 1 P TENTHSOUT_2_OBUF $end
$var wire 1 Q TENTHSOUT_0_OBUF $end
$var wire 1 R TENTHSOUT_1_OBUF $end
$var wire 1 S TENTHSOUT_3_OBUF $end
$var wire 1 T TENTHSOUT_4_OBUF $end
$var wire 1 U TENTHSOUT_5_OBUF $end
$var wire 1 V TENTHSOUT_6_OBUF $end
$var wire 1 W TENTHSOUT_7_OBUF $end
$var wire 1 X TENSOUT_0_OBUF $end
$var wire 1 Y TENTHSOUT_8_OBUF $end
$var wire 1 Z TENSOUT_1_OBUF $end
$var wire 1 [ TENTHSOUT_9_OBUF $end
$var wire 1 \ TENSOUT_2_OBUF $end
$var wire 1 ] ONESOUT_0_OBUF $end
$var wire 1 ^ TENSOUT_3_OBUF $end
$var wire 1 _ ONESOUT_1_OBUF $end
$var wire 1 ` TENSOUT_4_OBUF $end
$var wire 1 a ONESOUT_2_OBUF $end
$var wire 1 b TENSOUT_5_OBUF $end
$var wire 1 c TENSOUT_6_OBUF $end
$var wire 1 d ONESOUT_3_OBUF $end
$var wire 1 e ONESOUT_4_OBUF $end
$var wire 1 f ONESOUT_5_OBUF $end
$var wire 1 g ONESOUT_6_OBUF $end
$var wire 1 h Inst_dcm1_CLKIN_IBUFG_OUT $end
$var wire 1 i RESET_IBUF $end
$var wire 1 j STRTSTOP_IBUF $end
$var wire 1 k dcm_lock $end
$var wire 1 l Inst_dcm1_CLK0_BUF $end
$var wire 1 m GLOBAL_LOGIC1 $end
$var wire 1 n sixty_msbce_SW0/O $end
$var wire 1 o sixty_msbce $end
$var wire 1 p cnt60enable $end
$var wire 1 q sixty_msbclr $end
$var wire 1 r MACHINE_current_state_FFd2 $end
$var wire 1 s MACHINE_current_state_FFd1 $end
$var wire 1 t MACHINE_current_state_FFd2-In $end
$var wire 1 u MACHINE_current_state_FFd1-In $end
$var wire 1 v MACHINE_current_state_FFd4 $end
$var wire 1 w MACHINE_current_state_FFd3-In $end
$var wire 1 x MACHINE_current_state_FFd5 $end
$var wire 1 y MACHINE_current_state_FFd5-In $end
$var wire 1 z N1455 $end
$var wire 1 { N1561 $end
$var wire 1 | MACHINE_current_state_FFd4-In $end
$var wire 1 } GLOBAL_LOGIC1_0 $end
$var wire 1 ~ GLOBAL_LOGIC1_1 $end
$var wire 1 !! GLOBAL_LOGIC1_2 $end
$var wire 1 "! GSR $end
$var wire 1 #! GTS $end
$var wire 1 $! xcounter/N6/DXMUX $end
$var wire 1 %! xcounter/N6/F $end
$var wire 1 &! xcounter/N6/G $end
$var wire 1 '! xcounter/N6/CLKINV $end
$var wire 1 (! xcounter/N6/CEINV $end
$var wire 1 )! xtermcnt/DYMUX $end
$var wire 1 *! xtermcnt/G $end
$var wire 1 +! xtermcnt/CLKINV $end
$var wire 1 ,! xtermcnt/CEINV $end
$var wire 1 -! xcounter/N2/XORF $end
$var wire 1 .! xcounter/N2/CYINIT $end
$var wire 1 /! xcounter/N2/CY0F $end
$var wire 1 0! xcounter/N2/CYSELF $end
$var wire 1 1! xcounter/N120 $end
$var wire 1 2! xcounter/N2/BXINVNOT $end
$var wire 1 3! xcounter/N2/CYMUXG $end
$var wire 1 4! xcounter/N2/LOGIC_ONE $end
$var wire 1 5! xcounter/N122_rt $end
$var wire 1 6! xcounter/N2/G $end
$var wire 1 7! xcounter/N3/XORF $end
$var wire 1 8! xcounter/N3/CYINIT $end
$var wire 1 9! xcounter/N3/CY0F $end
$var wire 1 :! xcounter/N125 $end
$var wire 1 ;! xcounter/N3/XORG $end
$var wire 1 <! xcounter/N127 $end
$var wire 1 =! xcounter/N3/CYSELF $end
$var wire 1 >! xcounter/N3/CYMUXFAST $end
$var wire 1 ?! xcounter/N3/CYAND $end
$var wire 1 @! xcounter/N3/FASTCARRY $end
$var wire 1 A! xcounter/N3/CYMUXG2 $end
$var wire 1 B! xcounter/N3/CYMUXF2 $end
$var wire 1 C! xcounter/N3/CY0G $end
$var wire 1 D! xcounter/N3/CYSELG $end
$var wire 1 E! xcounter/N130 $end
$var wire 1 F! xcounter/N5/XORF $end
$var wire 1 G! xcounter/N5/CYINIT $end
$var wire 1 H! xcounter/N135 $end
$var wire 1 I! xcounter/N5/G $end
$var wire 1 J! Q<0>/DYMUX $end
$var wire 1 K! Q<0>/G $end
$var wire 1 L! Q<0>/SRFFMUX $end
$var wire 1 M! Q<0>/CLKINV $end
$var wire 1 N! Q<0>/CEINV $end
$var wire 1 O! Q<1>/DXMUX $end
$var wire 1 P! Q<1>/F $end
$var wire 1 Q! Q<1>/DYMUX $end
$var wire 1 R! Q<1>/G $end
$var wire 1 S! Q<1>/SRFFMUX $end
$var wire 1 T! Q<1>/CLKINV $end
$var wire 1 U! Q<1>/CEINV $end
$var wire 1 V! Q<3>/DYMUX $end
$var wire 1 W! Q<3>/G $end
$var wire 1 X! Q<3>/CLKINV $end
$var wire 1 Y! Q<3>/CEINV $end
$var wire 1 Z! TENTHSOUT<0>/ENABLE $end
$var wire 1 [! TENTHSOUT<0>/GTS_OR_T $end
$var wire 1 \! TENTHSOUT<0>/O $end
$var wire 1 ]! TENTHSOUT<1>/ENABLE $end
$var wire 1 ^! TENTHSOUT<1>/GTS_OR_T $end
$var wire 1 _! TENTHSOUT<1>/O $end
$var wire 1 `! xcounter/N6/FFX/RST $end
$var wire 1 a! xcounter/N6/FFX/RSTAND $end
$var wire 1 b! TENTHSOUT<2>/ENABLE $end
$var wire 1 c! TENTHSOUT<2>/GTS_OR_T $end
$var wire 1 d! TENTHSOUT<2>/O $end
$var wire 1 e! TENTHSOUT<3>/ENABLE $end
$var wire 1 f! TENTHSOUT<3>/GTS_OR_T $end
$var wire 1 g! TENTHSOUT<3>/O $end
$var wire 1 h! TENTHSOUT<4>/ENABLE $end
$var wire 1 i! TENTHSOUT<4>/GTS_OR_T $end
$var wire 1 j! TENTHSOUT<4>/O $end
$var wire 1 k! TENTHSOUT<5>/ENABLE $end
$var wire 1 l! TENTHSOUT<5>/GTS_OR_T $end
$var wire 1 m! TENTHSOUT<5>/O $end
$var wire 1 n! TENTHSOUT<6>/ENABLE $end
$var wire 1 o! TENTHSOUT<6>/GTS_OR_T $end
$var wire 1 p! TENTHSOUT<6>/O $end
$var wire 1 q! TENTHSOUT<7>/ENABLE $end
$var wire 1 r! TENTHSOUT<7>/GTS_OR_T $end
$var wire 1 s! TENTHSOUT<7>/O $end
$var wire 1 t! TENSOUT<0>/ENABLE $end
$var wire 1 u! TENSOUT<0>/GTS_OR_T $end
$var wire 1 v! TENSOUT<0>/O $end
$var wire 1 w! TENTHSOUT<8>/ENABLE $end
$var wire 1 x! TENTHSOUT<8>/GTS_OR_T $end
$var wire 1 y! TENTHSOUT<8>/O $end
$var wire 1 z! TENSOUT<1>/ENABLE $end
$var wire 1 {! TENSOUT<1>/GTS_OR_T $end
$var wire 1 |! TENSOUT<1>/O $end
$var wire 1 }! TENTHSOUT<9>/ENABLE $end
$var wire 1 ~! TENTHSOUT<9>/GTS_OR_T $end
$var wire 1 !" TENTHSOUT<9>/O $end
$var wire 1 "" TENSOUT<2>/ENABLE $end
$var wire 1 #" TENSOUT<2>/GTS_OR_T $end
$var wire 1 $" TENSOUT<2>/O $end
$var wire 1 %" ONESOUT<0>/ENABLE $end
$var wire 1 &" ONESOUT<0>/GTS_OR_T $end
$var wire 1 '" ONESOUT<0>/O $end
$var wire 1 (" TENSOUT<3>/ENABLE $end
$var wire 1 )" TENSOUT<3>/GTS_OR_T $end
$var wire 1 *" TENSOUT<3>/O $end
$var wire 1 +" ONESOUT<1>/ENABLE $end
$var wire 1 ," ONESOUT<1>/GTS_OR_T $end
$var wire 1 -" ONESOUT<1>/O $end
$var wire 1 ." TENSOUT<4>/ENABLE $end
$var wire 1 /" TENSOUT<4>/GTS_OR_T $end
$var wire 1 0" TENSOUT<4>/O $end
$var wire 1 1" ONESOUT<2>/ENABLE $end
$var wire 1 2" ONESOUT<2>/GTS_OR_T $end
$var wire 1 3" ONESOUT<2>/O $end
$var wire 1 4" TENSOUT<5>/ENABLE $end
$var wire 1 5" TENSOUT<5>/GTS_OR_T $end
$var wire 1 6" TENSOUT<5>/O $end
$var wire 1 7" xtermcnt/FFY/RST $end
$var wire 1 8" TENSOUT<6>/ENABLE $end
$var wire 1 9" TENSOUT<6>/GTS_OR_T $end
$var wire 1 :" TENSOUT<6>/O $end
$var wire 1 ;" ONESOUT<3>/ENABLE $end
$var wire 1 <" ONESOUT<3>/GTS_OR_T $end
$var wire 1 =" ONESOUT<3>/O $end
$var wire 1 >" ONESOUT<4>/ENABLE $end
$var wire 1 ?" ONESOUT<4>/GTS_OR_T $end
$var wire 1 @" ONESOUT<4>/O $end
$var wire 1 A" ONESOUT<5>/ENABLE $end
$var wire 1 B" ONESOUT<5>/GTS_OR_T $end
$var wire 1 C" ONESOUT<5>/O $end
$var wire 1 D" ONESOUT<6>/ENABLE $end
$var wire 1 E" ONESOUT<6>/GTS_OR_T $end
$var wire 1 F" ONESOUT<6>/O $end
$var wire 1 G" CLK/INBUF $end
$var wire 1 H" RESET/INBUF $end
$var wire 1 I" STRTSTOP/INBUF $end
$var wire 1 J" Inst_dcm1_DCM_INST/STATUS0 $end
$var wire 1 K" Inst_dcm1_DCM_INST/STATUS1 $end
$var wire 1 L" Inst_dcm1_DCM_INST/STATUS2 $end
$var wire 1 M" Inst_dcm1_DCM_INST/STATUS3 $end
$var wire 1 N" Inst_dcm1_DCM_INST/STATUS4 $end
$var wire 1 O" Inst_dcm1_DCM_INST/STATUS5 $end
$var wire 1 P" Inst_dcm1_DCM_INST/STATUS6 $end
$var wire 1 Q" Inst_dcm1_DCM_INST/STATUS7 $end
$var wire 1 R" Inst_dcm1_DCM_INST/PSDONE $end
$var wire 1 S" Inst_dcm1_DCM_INST/CLKFX180 $end
$var wire 1 T" Inst_dcm1_DCM_INST/CLKFX $end
$var wire 1 U" Inst_dcm1_DCM_INST/CLKDV $end
$var wire 1 V" Inst_dcm1_DCM_INST/CLK2X180 $end
$var wire 1 W" Inst_dcm1_DCM_INST/CLK2X $end
$var wire 1 X" Inst_dcm1_DCM_INST/CLK270 $end
$var wire 1 Y" Inst_dcm1_DCM_INST/CLK180 $end
$var wire 1 Z" Inst_dcm1_DCM_INST/CLK90 $end
$var wire 1 [" Inst_dcm1_DCM_INST/PSCLKINVNOT $end
$var wire 1 \" Inst_dcm1_DCM_INST/PSENINVNOT $end
$var wire 1 ]" Inst_dcm1_DCM_INST/PSINCDECINVNOT $end
$var wire 1 ^" Inst_dcm1_DCM_INST/DSSENINVNOT $end
$var wire 1 _" Inst_dcm1_DCM_INST/CLKFB_BUF $end
$var wire 1 `" Inst_dcm1_DCM_INST/CLKIN_BUF $end
$var wire 1 a" Inst_dcm1_CLK0_BUFG_INST/S_INVNOT $end
$var wire 1 b" sixty_msbce/F $end
$var wire 1 c" sixty_msbce/G $end
$var wire 1 d" sixty_lsbcount_QOUT<3>/DXMUX $end
$var wire 1 e" sixty_lsbcount_QOUT<3>/F $end
$var wire 1 f" sixty_lsbcount_QOUT<3>/DYMUX $end
$var wire 1 g" sixty_lsbcount_QOUT<3>/G $end
$var wire 1 h" sixty_lsbcount_QOUT<3>/SRFFMUX $end
$var wire 1 i" sixty_lsbcount_QOUT<3>/CLKINV $end
$var wire 1 j" sixty_lsbcount_QOUT<3>/CEINV $end
$var wire 1 k" sixty_msbcount_QOUT<3>/DXMUX $end
$var wire 1 l" sixty_msbcount_QOUT<3>/F $end
$var wire 1 m" sixty_msbcount_QOUT<3>/DYMUX $end
$var wire 1 n" sixty_msbcount_QOUT<3>/G $end
$var wire 1 o" sixty_msbcount_QOUT<3>/SRFFMUX $end
$var wire 1 p" sixty_msbcount_QOUT<3>/CLKINV $end
$var wire 1 q" sixty_msbcount_QOUT<3>/CEINV $end
$var wire 1 r" MACHINE_current_state_FFd2/DXMUX $end
$var wire 1 s" MACHINE_current_state_FFd2/F $end
$var wire 1 t" MACHINE_current_state_FFd2/DYMUX $end
$var wire 1 u" MACHINE_current_state_FFd2/G $end
$var wire 1 v" MACHINE_current_state_FFd2/SRFFMUX $end
$var wire 1 w" MACHINE_current_state_FFd2/CLKINV $end
$var wire 1 x" MACHINE_current_state_FFd3/F $end
$var wire 1 y" MACHINE_current_state_FFd3/DYMUX $end
$var wire 1 z" MACHINE_current_state_FFd3/G $end
$var wire 1 {" MACHINE_current_state_FFd3/CLKINV $end
$var wire 1 |" MACHINE_current_state_FFd6/DXMUX $end
$var wire 1 }" MACHINE_current_state_FFd6/BXINVNOT $end
$var wire 1 ~" MACHINE_current_state_FFd6/DYMUX $end
$var wire 1 !# MACHINE_current_state_FFd6/G $end
$var wire 1 "# MACHINE_current_state_FFd6/SRFFMUX $end
$var wire 1 ## MACHINE_current_state_FFd6/CLKINV $end
$var wire 1 $# TENTHSOUT_3_OBUF/F $end
$var wire 1 %# TENTHSOUT_3_OBUF/G $end
$var wire 1 &# TENTHSOUT_4_OBUF/F $end
$var wire 1 '# TENTHSOUT_4_OBUF/G $end
$var wire 1 (# sixty_lsbcount_QOUT<0>/DXMUX $end
$var wire 1 )# sixty_lsbcount_QOUT<0>/F $end
$var wire 1 *# sixty_lsbcount_QOUT<0>/BXINVNOT $end
$var wire 1 +# sixty_lsbcount_QOUT<0>/DYMUX $end
$var wire 1 ,# sixty_lsbcount_QOUT<0>/G $end
$var wire 1 -# sixty_lsbcount_QOUT<0>/SRFFMUX $end
$var wire 1 .# sixty_lsbcount_QOUT<0>/CLKINV $end
$var wire 1 /# sixty_lsbcount_QOUT<0>/CEINV $end
$var wire 1 0# TENSOUT_2_OBUF/F $end
$var wire 1 1# TENSOUT_2_OBUF/G $end
$var wire 1 2# TENSOUT_6_OBUF/F $end
$var wire 1 3# TENSOUT_6_OBUF/G $end
$var wire 1 4# TENSOUT_5_OBUF/F $end
$var wire 1 5# TENSOUT_5_OBUF/G $end
$var wire 1 6# sixty_msbcount_QOUT<1>/DXMUX $end
$var wire 1 7# sixty_msbcount_QOUT<1>/F $end
$var wire 1 8# sixty_msbcount_QOUT<1>/DYMUX $end
$var wire 1 9# sixty_msbcount_QOUT<1>/G $end
$var wire 1 :# sixty_msbcount_QOUT<1>/BYINVNOT $end
$var wire 1 ;# sixty_msbcount_QOUT<1>/SRFFMUX $end
$var wire 1 <# sixty_msbcount_QOUT<1>/CLKINV $end
$var wire 1 =# sixty_msbcount_QOUT<1>/CEINV $end
$var wire 1 ># sixty_msbclr/F $end
$var wire 1 ?# sixty_msbclr/G $end
$var wire 1 @# ONESOUT_2_OBUF/F $end
$var wire 1 A# ONESOUT_2_OBUF/G $end
$var wire 1 B# ONESOUT_6_OBUF/F $end
$var wire 1 C# ONESOUT_6_OBUF/G $end
$var wire 1 D# ONESOUT_5_OBUF/F $end
$var wire 1 E# ONESOUT_5_OBUF/G $end
$var wire 1 F# TENTHSOUT_5_OBUF/F $end
$var wire 1 G# TENTHSOUT_5_OBUF/G $end
$var wire 1 H# TENTHSOUT_6_OBUF/F $end
$var wire 1 I# TENTHSOUT_6_OBUF/G $end
$var wire 1 J# MACHINE_current_state_FFd4/DXMUX $end
$var wire 1 K# MACHINE_current_state_FFd4/F $end
$var wire 1 L# MACHINE_current_state_FFd4/G $end
$var wire 1 M# MACHINE_current_state_FFd4/CLKINV $end
$var wire 1 N# TENTHSOUT_7_OBUF/G $end
$var wire 1 O# sixty_lsbcount_QOUT<0>/FFY/RST $end
$var wire 1 P# sixty_lsbcount_QOUT<0>/FFX/RST $end
$var wire 1 Q# Q<0>/FFY/SET $end
$var wire 1 R# Q<1>/FFY/RST $end
$var wire 1 S# Q<1>/FFX/RST $end
$var wire 1 T# Q<3>/FFY/RST $end
$var wire 1 U# Q<3>/FFY/RSTAND $end
$var wire 1 V# MACHINE_current_state_FFd2/FFY/RST $end
$var wire 1 W# MACHINE_current_state_FFd2/FFX/RST $end
$var wire 1 X# MACHINE_current_state_FFd3/FFY/RST $end
$var wire 1 Y# MACHINE_current_state_FFd3/FFY/RSTAND $end
$var wire 1 Z# MACHINE_current_state_FFd6/FFY/RST $end
$var wire 1 [# MACHINE_current_state_FFd6/FFX/SET $end
$var wire 1 \# MACHINE_current_state_FFd4/FFX/RST $end
$var wire 1 ]# MACHINE_current_state_FFd4/FFX/RSTAND $end
$var wire 1 ^# sixty_lsbcount_QOUT<3>/FFY/RST $end
$var wire 1 _# sixty_lsbcount_QOUT<3>/FFX/RST $end
$var wire 1 `# sixty_msbcount_QOUT<3>/FFY/RST $end
$var wire 1 a# sixty_msbcount_QOUT<3>/FFX/RST $end
$var wire 1 b# sixty_msbcount_QOUT<1>/FFY/RST $end
$var wire 1 c# sixty_msbcount_QOUT<1>/FFX/RST $end
$var wire 1 d# VCC $end
$var wire 1 e# NLW_xcounter/N2/CYMUXG_IA_UNCONNECTED $end
$var wire 1 f# GND $end
$var wire 1 g# Q [3] $end
$var wire 1 h# Q [2] $end
$var wire 1 i# Q [1] $end
$var wire 1 j# Q [0] $end
$var wire 1 k# sixty_lsbcount_QOUT [3] $end
$var wire 1 l# sixty_lsbcount_QOUT [2] $end
$var wire 1 m# sixty_lsbcount_QOUT [1] $end
$var wire 1 n# sixty_lsbcount_QOUT [0] $end
$var wire 1 o# sixty_lsbcount_QOUT__n0001 [3] $end
$var wire 1 p# sixty_lsbcount_QOUT__n0001 [2] $end
$var wire 1 q# sixty_lsbcount_QOUT__n0001 [1] $end
$var wire 1 r# sixty_msbcount_QOUT [3] $end
$var wire 1 s# sixty_msbcount_QOUT [2] $end
$var wire 1 t# sixty_msbcount_QOUT [1] $end
$var wire 1 u# sixty_msbcount_QOUT [0] $end
$var wire 1 v# sixty_msbcount_QOUT__n0001 [3] $end
$var wire 1 w# sixty_msbcount_QOUT__n0001 [2] $end
$var wire 1 x# sixty_msbcount_QOUT__n0001 [1] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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