test_i2c_to_gpio.dmp

I2C to GPIO Port expander的Verilog HDL 程序原码

$date
	Tue Nov 20 11:26:44 2007
$end
$version
	ModelSim Version 6.1g
$end
$timescale
	10ns
$end
$scope module test_I2C_to_GPIO $end
$var parameter 0 ! tdelay $end
$var parameter 0 " testcycle $end
$var reg 1 # sclk $end
$var reg 8 $ GPIO_input [7:0] $end
$var reg 1 % start_t $end
$var reg 1 & sda_in $end
$var reg 1 ' ack_check $end
$var reg 1 ( GPIO_input_check $end
$var reg 1 ) read_oper_check $end
$var reg 1 * write_oper_check $end
$var reg 1 + slave_add_check $end
$var wand 1 , sda $end
$var wire 1 - GPIO_input_reg [7] $end
$var wire 1 . GPIO_input_reg [6] $end
$var wire 1 / GPIO_input_reg [5] $end
$var wire 1 0 GPIO_input_reg [4] $end
$var wire 1 1 GPIO_input_reg [3] $end
$var wire 1 2 GPIO_input_reg [2] $end
$var wire 1 3 GPIO_input_reg [1] $end
$var wire 1 4 GPIO_input_reg [0] $end
$var wire 1 5 GPIO_output [7] $end
$var wire 1 6 GPIO_output [6] $end
$var wire 1 7 GPIO_output [5] $end
$var wire 1 8 GPIO_output [4] $end
$var wire 1 9 GPIO_output [3] $end
$var wire 1 : GPIO_output [2] $end
$var wire 1 ; GPIO_output [1] $end
$var wire 1 < GPIO_output [0] $end
$var wire 1 = count [3] $end
$var wire 1 > count [2] $end
$var wire 1 ? count [1] $end
$var wire 1 @ count [0] $end
$var reg 8 A GPIO_input_store [7:0] $end
$var reg 8 B GPIO_output_send [7:0] $end
$var reg 7 C slave_add_compare [6:0] $end
$var integer 32 D i $end
$var integer 32 E r_seed $end
$scope module test $end
$var parameter 7 F slave_address $end
$var parameter 32 G n $end
$var wire 1 , sda $end
$var wire 1 H sclk $end
$var wire 1 I GPIO_input [7] $end
$var wire 1 J GPIO_input [6] $end
$var wire 1 K GPIO_input [5] $end
$var wire 1 L GPIO_input [4] $end
$var wire 1 M GPIO_input [3] $end
$var wire 1 N GPIO_input [2] $end
$var wire 1 O GPIO_input [1] $end
$var wire 1 P GPIO_input [0] $end
$var reg 8 Q GPIO_output [7:0] $end
$var reg 1 R start_stop $end
$var reg 1 S start $end
$var reg 1 T stop $end
$var reg 1 U some_other_device $end
$var reg 1 V repeat_start $end
$var reg 1 W write_flag $end
$var reg 1 X reset $end
$var reg 1 Y sda_out $end
$var reg 1 Z done $end
$var reg 4 [ count [3:0] $end
$var reg 8 \ GPIO_input_reg [7:0] $end
$var reg 1 ] data_or_address $end
$var reg 1 ^ sda_ack $end
$var reg 1 _ read_oper $end
$var reg 1 ` add_is_matching $end
$var wire 1 a sda_is_ack $end
$var wire 1 b ack_flag $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
r3.5 !
r100 "
b0 F
b1000 G
0#
bx $
x%
x&
x'
x(
x)
x*
x+
bx A
bx B
bx C
b0 D
b10 E
bx Q
xR
xS
xT
xU
0V
xW
0X
xY
xZ
bx [
bx \
x]
x^
x_
x`
x,
z4
z3
z2
z1
z0
z/
z.
z-
x<
x;
x:
x9
x8
x7
x6
x5
z@
z?
z>
z=
xa
xb
xP
xO
xN
xM
xL
xK
xJ
xI
0H
$end
#500
1#
1H
1`
0^
0]
0U
0W
0Z
#1000
0#
0H
#1350
1&
#1500
1#
1H
#1700
0&
b100001101110011011 E
b0 C
0,
1S
#2000
0#
0H
1R
1X
b111 [
0a
1b
0T
0S
#2500
1#
1H
#3000
0#
0H
0X
b110 [
zY
#3500
1#
1H
#4000
0#
0H
b101 [
#4500
1#
1H
#5000
0#
0H
b100 [
#5500
1#
1H
#6000
0#
0H
b11 [
#6500
1#
1H
#7000
0#
0H
b10 [
#7500
1#
1H
#8000
0#
0H
b1 [
#8500
1#
1H
#9000
0#
0H
b0 [
0b
#9050
1&
1,
#9500
1#
1H
1_
1]
#10000
0#
0H
b1111 [
0Y
0,
1a
1b
#10050
1+
#10500
1#
1H
1^
1W
#11000
0#
0H
b111 [
zY
bx0 \
1,
0a
#11050
0+
#11500
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#12000
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0H
b110 [
bx00 \
#12500
1#
1H
#13000
0#
0H
b101 [
bx000 \
#13500
1#
1H
#14000
0#
0H
b100 [
bx0000 \
#14500
1#
1H
#15000
0#
0H
b11 [
bx00000 \
#15500
1#
1H
#16000
0#
0H
b10 [
bx000000 \
#16500
1#
1H
#17000
0#
0H
b1 [
bx0000000 \
#17500
1#
1H
#18000
0#
0H
b0 [
b0 \
0b
#18500
1#
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1Z
#19000
0#
0H
b1111 [
1a
1b
#19500
1#
1H
1^
#20000
0#
0H
b111 [
0a
#20500
1#
1H
0^
#21000
0#
0H
b110 [
#21500
1#
1H
#22000
0#
0H
b101 [
#22500
1#
1H
#22700
0&
0,
1S
#23000
0#
0H
1V
1X
b111 [
0S
#23500
1#
1H
0]
0W
0Z
#24000
0#
0H
0X
0V
b110 [
#24500
1#
1H
#25000
0#
0H
b101 [
#25500
1#
1H
#26000
0#
0H
b100 [
#26500
1#
1H
#27000
0#
0H
b11 [
#27500
1#
1H
#28000
0#
0H
b10 [
#28500
1#
1H
#29000
0#
0H
b1 [
#29500
1#
1H
#30000
0#
0H
b0 [
0b
#30500
1#
1H
0_
1]
#31000
0#
0H
b1111 [
0Y
1a
1b
#31050
1&
b111000101100011111101000100000 E
1'
b1110001 B
#31500
1#
1H
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0#
0H
b111 [
zY
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#32050
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0,
#32500
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b0xxxxxxx Q
05
#33000
0#
0H
b110 [
#33050
1&
1,
#33500
1#
1H
b1xxxxxx Q
16
#34000
0#
0H
b101 [
#34500
1#
1H
b11xxxxx Q
17
#35000
0#
0H
b100 [
#35500
1#
1H
b111xxxx Q
18
#36000
0#
0H
b11 [
#36050
0&
0,
#36500
1#
1H
b1110xxx Q
09
#37000
0#
0H
b10 [
#37500
1#
1H
b11100xx Q
0:
#38000
0#
0H
b1 [
#38500
1#
1H
b111000x Q
0;
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0b
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1,
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1Z
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b1111 [
0Y
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#41000
0#
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b111 [
zY
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#41050
0*
#41500
1#
1H
0^
#42000
0#
0H
b110 [
#42500
1#
1H
#43000
0#
0H
b101 [
#43500
1#
1H
#44000
0#
0H
b100 [
#44500
1#
1H
#45000
0#
0H
b11 [
#45500
1#
1H
#46000
0#
0H
b10 [
#46500
1#
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#47000
0#
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b1 [
#47500
1#
1H
#48000
0#
0H
b0 [
0b
#48500
1#
1H
#49000
0#
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b1111 [
0Y
0,
1a
1b
#49500
1#
1H
1^
#50000
0#
0H
b111 [
zY
1,
0a
#50500
1#
1H
0^
#51000
0#
0H
b110 [
#51500
1#
1H
#52000
0#
0H
b101 [
#52500
1#
1H
#52700
0&
0,
1S
#53000
0#
0H
1V
1X
b111 [
0S
#53500
1#
1H
0]
0Z
#54000
0#
0H
0X
0V
b110 [
#54500
1#
1H
#55000
0#
0H
b101 [
#55500
1#
1H
#56000
0#
0H
b100 [
#56500
1#
1H
#57000
0#
0H
b11 [
#57500
1#
1H
#58000
0#
0H
b10 [
#58500
1#
1H
#59000
0#
0H
b1 [
#59500
1#
1H
#60000
0#
0H
b0 [
0b
#60200
b1101010010110001110101110100001 E
b11010100 $
0P
0O
1N
0M
1L
0K
1J
1I
1&
1,
#60500
1#
1H
1_
1]
#60700
1'
#61000
0#
0H
b1111 [
0Y
b11010100 \
0,
1a
1b
#61500
1#
1H
1^
1W
#61700
0'
#62000
0#
0H
b111 [
zY
b10101000 \
1,
0a
#62500
1#
1H
0^
#62700
b1xxxxxxx A
#63000
0#
0H
b110 [
b1010000 \
#63500
1#
1H
#63700
b11xxxxxx A
#64000
0#
0H
b101 [
0Y
b10100000 \
0,
#64500
1#
1H
#64700
b110xxxxx A
#65000
0#
0H
b100 [
zY
b1000000 \
1,
#65500
1#
1H
#65700
b1101xxxx A
#66000
0#
0H
b11 [
0Y
b10000000 \
0,
#66500
1#
1H
#66700
b11010xxx A
#67000
0#
0H
b10 [
zY
b0 \
1,
#67500
1#
1H
#67700
b110101xx A
#68000
0#
0H
b1 [
0Y
0,
#68500
1#
1H
#68700
b1101010x A
#69000
0#
0H
b0 [
0b
#69500
1#
1H
1Z
#69700
b11010100 A
#70000
0#
0H
b1111 [
zY
1,
1a
1b
#70500
1#
1H
1^
#70700
1)
#71000
0#
0H
b111 [
0a
#71500
1#
1H
0^
#71700
0)
#72000
0#
0H
b110 [
#72500
1#
1H
#73000
0#
0H
b101 [
#73500
1#
1H
#74000
0#
0H
b100 [
#74500
1#
1H
#75000
0#
0H
b11 [
#75500
1#
1H
#76000
0#
0H
b10 [
#76500
1#
1H
#77000
0#
0H
b1 [
#77500
1#
1H
#78000
0#
0H
b0 [
0b
#78500
1#
1H
#79000
0#
0H
b1111 [
1a
1b
#79500
1#
1H
1^
#80000
0#
0H
b111 [
0a
#80500
1#
1H
0^
#81000
0#
0H
b110 [
#81500
1#
1H
#82000
0#
0H
b101 [
#82350
0&
0,
#82500
1#
1H
#82700
1&
1,
1T
#83000
0#
0H
0R
1X
b100 [
0T
#83500
1#
1H
0]
0W
0Z