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基于verilog hdl的UART串口发送子程序。

# Reading D:/altera/90/modelsim_ae/tcl/vsim/pref.tcl 
# OpenFile {F:/My   Project/Verilog HDL/UART/uart_txd/uart.mpf} 
# Loading project uart
vsim -voptargs=+acc work.uart_txd_vlg_check_tst
# vsim -voptargs=+acc work.uart_txd_vlg_check_tst 
# //  ModelSim ALTERA 6.4a Oct 22 2008 
# //
# //  Copyright 1991-2008 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.uart_txd_vlg_check_tst
view wave
# .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
vsim -voptargs=+acc work.uart_txd_vlg_check_tst
# vsim -voptargs=+acc work.uart_txd_vlg_check_tst 
# Loading work.uart_txd_vlg_check_tst
toggle add \
{sim:/uart_txd_vlg_check_tst/clk_out } 
# ** Error: (vsim-43) toggle coverage is not supported in this version.
# 
force -freeze sim:/uart_txd_vlg_check_tst/clk_out 1 10, 0 {60 ps} -r 100
add wave sim:/uart_txd_vlg_check_tst/*