代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/18597/796623

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# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # do test.fdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # --
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www.eeworm.com/read/450152/1672233

mti or1200.cr.mti

../../../rtl/verilog/or1200_spram_64x22.v {1 {vlog -work work +incdir+../../../rtl/verilog +incdir+../../../bench/verilog ../../../rtl/verilog/or1200_spram_64x22.v Model Technology ModelSim SE vlog 6
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www.eeworm.com/read/195019/8178130

do func_sim.do

# 8b/10b Functional Simulation ModelSim DO file # Create work library vlib work # Compile package files vcom -just e -93 -explicit -work work pkg_convert.vhd vcom -skip e -93 -explicit -wor
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www.eeworm.com/read/235010/14089034

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# Reading D:/Modeltech_xe/tcl/vsim/pref.tcl # do test_ddr_command.ndo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE III vlog 6.1e Compiler 2006.03 Mar
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www.eeworm.com/read/202635/15377442

do func_sim.do

# 16b/20b Functional Simulation ModelSim DO file # Create work library vlib work # Compile package files vcom -just e -93 -explicit -work work pkg_convert.vhd vcom -skip e -93 -explicit -wo
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www.eeworm.com/read/187841/8596613

do post_sim.do

# 16b/20b Post Route Timing Simulation ModelSim DO file # Create work library vlib work # Compile package files vcom -just e -93 -explicit -work work pkg_convert.vhd vcom -skip e -93 -explic
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www.eeworm.com/read/381474/9090666

mti uart_module.cr.mti

C:/Modeltech_6.0/myproject/Uartmodule/Uart_rx.v {1 {vlog -work work C:/Modeltech_6.0/myproject/Uartmodule/Uart_rx.v Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004 -- Compiling mo
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www.eeworm.com/read/168700/9901626

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# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # do t_divider.fdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 1
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www.eeworm.com/read/469049/6984337

vcd risc8.vcd

$date Thu Apr 30 20:34:59 2009 $end $version ModelSim Version 6.4a $end $timescale 10ps $end $scope module cpu_test $end $var parameter 32 ! CLKHI $end $var parameter 32 " CLKLO $end $v
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www.eeworm.com/read/468520/6992244

mti siva.cr.mti

D:/myhdl/and3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/and3.vhd Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008 -- Loading package standard -- Loading package std
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