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来自「这是我用vhdl语言」· 代码 · 共 42 行

# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl 
# do test.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dpram2
# -- Compiling architecture behavioral of dpram2
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity test
# -- Compiling architecture testbench_arch of test
# -- Loading entity dpram2
# -- Compiling configuration dpram2_cfg
# -- Loading entity test
# -- Loading architecture testbench_arch of test
# vsim -lib work -t 1ps test 
# Loading C:/Modeltech_xe/win32xoem/../std.standard
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body)
# Loading work.test(testbench_arch)
# Loading work.dpram2(behavioral)
# .wave
# .structure
# .signals
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 1210 ns  Iteration: 0  Process: /test/line__92 File: test.vhw
# Break at test.vhw line 219
# Simulation Breakpoint: Break at test.vhw line 219
# MACRO ./test.fdo PAUSED at line 13
destroy .wave