transcript

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do t_divider.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity devider
# -- Compiling architecture behavioral of devider
# Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity t_divider
# -- Compiling architecture testbench_arch of t_divider
# -- Loading entity devider
# -- Compiling configuration devider_cfg
# -- Loading entity t_divider
# -- Loading architecture testbench_arch of t_divider
# vsim -lib work -t 1ps t_divider 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
# Loading work.t_divider(testbench_arch)
# Loading work.devider(behavioral)
# .wave
# .structure
# .signals
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 1850 us  Iteration: 0  Process: /t_divider/line__55 File: t_divider.vhw
# Break at t_divider.vhw line 200
# Simulation Breakpoint: Break at t_divider.vhw line 200
# MACRO ./t_divider.fdo PAUSED at line 13