代码搜索：datapath
找到约 404 项符合「datapath」的源代码
代码结果 404
www.eeworm.com/read/452801/7432649
vhd m_datapath.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY M_datapath IS
PORT ( clk, samp_ena : IN STD_LOGIC ;
load_lopndn, load_resultn
www.eeworm.com/read/452801/7432650
scf m_datapath.scf
www.eeworm.com/read/450543/7482418
v datapath_fifo.v
//this file provide the datapath between pci and local-board.
//created by JAboy on 04-09-2007.
module datapath_fifo(
rstn,clk_pci,clk_local,flush,
/**************************
www.eeworm.com/read/406905/11432882
v datapath_snoop.v
`include "definitions.v"
// Produced by /usr/class/ee272/bin/snoopgen from file snoop.in
// Remember to run Verilog with -x if any variables are subscripted
// 2 Clock phases: phi1_b phi2_b
// In
www.eeworm.com/read/406095/11449403
vhd datapath_test.vhd
-- ============================================================
-- File Name: datapath_test.vhd
-- ============================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1
www.eeworm.com/read/480619/1316352
vhd datapath_struct.vhd
-- -----------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005-2008 HT-LAB
www.eeworm.com/read/426531/1989455
v datapath_d.v
%%% protect protected_file
%%% protect begin_protected
%%% protect encoding=(enctype=base64)
%%% protect key_keyowner=Synplicity
%%% protect key_keyname=SYNP05_001
%%% protect key_method=rsa
%%% prote
www.eeworm.com/read/300595/13903747
v div_datapath.v
module div_datapath(clk,reset,rdy,dividend,
divisor,run,wrg,fsh,quo,rem);
parameter n = 32;
parameter m = 16;
input clk,reset,rdy,run;
input [n-1:0] dividend,divisor;
www.eeworm.com/read/291878/8391383
v idwt97_datapath.v
//`timescale 1ns/10ps
module IDWT97_DataPath(
Clk,
Reset,
Sel,
indata,
outdata
);
parameter Data_Width = 20;
input Clk;
input Reset;
input [4:0] Sel;
input [Data_Width-1:0] indata;
outpu
www.eeworm.com/read/291878/8391441
v fdwt97_datapath.v
//`timescale 1ns/10ps
module FDWT97_DataPath(
Clk,
Reset,
Sel,
indata,
outdata
);
parameter Data_Width = 20;
input Clk;
input Reset;
input [4:0] Sel;
input [Data_Width-1:0] indata;
outpu