m_datapath.vhd

With shift add way to implement multiply harware circuit.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;

ENTITY M_datapath IS
	PORT ( clk, samp_ena             : IN    STD_LOGIC ;
	       load_lopndn, load_resultn : IN	STD_LOGIC ;
	       sr_mode                   : IN    STD_LOGIC_VECTOR( 1 DOWNTO 0) := "11" ;
	       output_lsbn, output_msbn  : IN    STD_LOGIC_VECTOR( 1 DOWNTO 0)  ;
		   databus                   : INOUT	STD_LOGIC_VECTOR( 7 DOWNTO 0) := "ZZZZZZZZ"  ) ;
END M_datapath ;

ARCHITECTURE structural OF M_datapath IS

-- use a_74157 component
component a_74157
	port (	gn: in STD_LOGIC;
		sel: in STD_LOGIC;
		a: in STD_LOGIC_VECTOR (4 downto 1);
		b: in STD_LOGIC_VECTOR (4 downto 1);
		y: out STD_LOGIC_VECTOR (4 downto 1));
end component;

-- use a_74283 component
component a_74283
	port (	a: in STD_LOGIC_VECTOR (4 downto 1);
		b: in STD_LOGIC_VECTOR (4 downto 1);
		cin: in STD_LOGIC;
		cout: out STD_LOGIC;
		sum: out STD_LOGIC_VECTOR (4 downto 1));
end component;

-- use j_74194 component
component j_74194 
	PORT ( clk, clrn, lin, rin	: IN	STD_LOGIC ;
	       s                    : IN    STD_LOGIC_vector( 1 downto 0) := "11" ;
           a,  b, c, d          : IN    STD_LOGIC ;
	       qa, qb, qc, qd       : OUT   STD_LOGIC );
END component ;

-- use a_74273 component that supplied by Altera
component a_74273
	port (	clrn: in STD_LOGIC;
    		clk: in STD_LOGIC;
	    	d: in STD_LOGIC_VECTOR (8 downto 1);
		    q: out STD_LOGIC_VECTOR (8 downto 1));
end component;

-- use a_74377 component that supplied by Altera
component a_74377
	port (	en: in STD_LOGIC;
		clk: in STD_LOGIC;
		d: in STD_LOGIC_VECTOR (8 downto 1);
		q: out STD_LOGIC_VECTOR (8 downto 1));
end component;

-- use j_tribus component that defined by Jue-Hsuan Hsiao  
component j_tribus  
 port( triout1 : in std_logic_vector(7 downto 0)  ;
       output_lsbn : in std_logic_vector( 1 downto 0)  ;
       triout2 : in std_logic_vector(7 downto 0)  ;
       output_msbn : in std_logic_vector( 1 downto 0)  ;
       tribus      : out std_logic_vector( 7 downto 0):="ZZZZZZZZ"  );
end component ;

signal hpbus, mcbus : std_logic_vector( 7 downto 0) :="ZZZZZZZZ" ;
signal sbus   : std_logic_vector( 7 downto 0) :="ZZZZZZZZ" ;
signal ind : std_logic_vector( 7 downto 0)  ;
signal f : std_logic_vector( 8 downto 0)  ;
signal s8, c4, selsum : std_logic ;
signal gnd, vcc : std_logic  ;
signal clkn,  samp_clk : std_logic  ;

BEGIN
gnd <= '0' ;
vcc <= '1' ;
clkn <= not clk ;
selsum <= ind(0) ;
samp_clk <= clkn and samp_ena ;
f(8) <= s8 and ind(0)  ;
 
u1 : a_74377 port map (load_lopndn, clkn, databus, mcbus) ;
u2a : j_74194 port map (clkn, vcc, gnd, f(0), sr_mode, databus(7), databus(6), databus(5),
                        databus(4), ind(7), ind(6), ind(5), ind(4)  );
u2b : j_74194 port map (clkn, vcc, gnd, ind(4), sr_mode, databus(3), databus(2), databus(1),
                        databus(0), ind(3), ind(2), ind(1), ind(0)  );

u3 : a_74273 port map (load_resultn, samp_clk, f( 8 downto 1) , hpbus) ;
u4 : a_74283 port map (hpbus(3 downto 0), mcbus(3 downto 0), gnd, c4, sbus(3 downto 0)) ;
u5 : a_74283 port map (hpbus(7 downto 4), mcbus(7 downto 4), c4, s8, sbus(7 downto 4)) ;
u6 : j_tribus port map (ind, output_lsbn, hpbus, output_msbn, databus) ;
u7 : a_74157 port map (gnd, selsum, hpbus(3 downto 0), sbus(3 downto 0), f(3 downto 0)) ;
u8 : a_74157 port map (gnd, selsum, hpbus(7 downto 4), sbus(7 downto 4), f(7 downto 4)) ;
     
END structural;