j_74194.vhd

来自「With shift add way to implement multiply」· VHDL 代码 · 共 41 行

-- MSI 74194 --shifter 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY j_74194 IS
	PORT ( clk, clrn, lin, rin	: IN	STD_LOGIC ;
	       s                    : IN    STD_LOGIC_vector( 1 downto 0) := "11" ;
           a,  b, c, d          : IN    STD_LOGIC ;
	       qa, qb, qc, qd       : OUT   STD_LOGIC );
END J_74194 ;

ARCHITECTURE behavioral OF j_74194 IS
signal  iq : std_logic_vector( 3 downto 0) := "ZZZZ" ;
BEGIN

process(clk, clrn) 
      begin
        if clrn = '0' then
          iq <= "00000000" ;
         else 
           if (clk'event and clk ='1') then
            case s is
              when "01" => iq <= rin & iq( 3 downto 1) ;  -- Shift to right
              when "10" => iq <= iq(2 downto 0) & lin ;   -- Shift to left
              when "11" => iq <= a & b & c & d ;
              when others => iq <= iq  ;
            end case ;
           end if ;
         end if ;
      end process  ;
      

 qa <= iq(3) ;
 qb <= iq(2) ;
 qc <= iq(1) ;
 qd <= iq(0) ;
 
END behavioral;