msi_mply.vhd

来自「With shift add way to implement multiply」· VHDL 代码 · 共 45 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY msi_mply IS
	PORT ( clk, start               : IN STD_LOGIC ;
	       done                     : OUT   STD_LOGIC ;
           --output_lsb, output_msb  : inout STD_LOGIC_VECTOR( 1 DOWNTO 0)  ;
           --load_resultn, load_lopndn, samp_ena : inout std_logic ;
		   databus           		: INOUT	STD_LOGIC_VECTOR( 7 DOWNTO 0) :="ZZZZZZZZ" ) ;
END msi_mply ;

ARCHITECTURE structural OF msi_mply IS

-- use m_datapath component
component m_datapath
	PORT ( clk, samp_ena                : IN    STD_LOGIC ;
	       load_lopndn, load_resultn	: IN	STD_LOGIC ;
	       sr_mode                      : IN    STD_LOGIC_VECTOR( 1 DOWNTO 0) := "11" ;
	       output_lsbn, output_msbn     : IN    STD_LOGIC_VECTOR( 1 DOWNTO 0)  ;
		   databus                      : INOUT	STD_LOGIC_VECTOR( 7 DOWNTO 0) := "ZZZZZZZZ"  ) ;
END component ;

-- use m_control component that defined by Jue-Hsuan Hsiao  
component M_control
	PORT ( clk, start                : IN  STD_LOGIC ;
	       output_lsb, output_msb     : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0):= "11"  ;
	       sr_mode                    : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0):= "00" ;
	       load_lopnd, load_result    : OUT STD_LOGIC := '1' ;
	       samp_ena, done          : OUT STD_LOGIC := '0' );
END component ;

signal sr_mode              :   STD_LOGIC_VECTOR( 1 DOWNTO 0) ;
signal output_lsb, output_msb     :  STD_LOGIC_VECTOR( 1 DOWNTO 0)  ;
signal load_resultn, load_lopndn, samp_ena : std_logic ;

BEGIN

data : M_datapath port map (clk, samp_ena, load_lopndn, load_resultn,  sr_mode, 
                output_lsb, output_msb,  databus ) ;
contol : M_control port map (clk, start ,output_lsb, output_msb, sr_mode,
	            load_lopndn, load_resultn, samp_ena, done  );
     
END structural;